Home
last modified time | relevance | path

Searched refs:RBX (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp83 BasePtr = Is64Bit ? X86::RBX : X86::ESI; in X86RegisterInfo()
90 case X86::EBX: case X86::RBX: return 1; in getCompactUnwindRegNum()
606 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
618 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
655 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
691 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
743 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
744 return X86::RBX; in getX86SubSuperRegister()
DX86RegisterInfo.td124 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
275 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
308 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
331 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
354 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
DX86CallingConv.td244 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
422 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
427 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
DX86FrameLowering.cpp405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in encodeCompactUnwindRegistersWithoutFrame()
473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in encodeCompactUnwindRegistersWithFrame()
DX86InstrSystem.td449 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
DX86InstrCompiler.td757 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
DX86InstrInfo.td1371 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
DX86ISelLowering.cpp11457 Regs64bit ? X86::RBX : X86::EBX, in ReplaceNodeResults()
16842 case X86::BX: DestReg = X86::RBX; break; in getRegForInlineAsmConstraint()
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h33 #define RBX 40 macro
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h164 ENTRY(RBX) \
182 ENTRY(RBX) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c101 GENOFFSET(AMD64,amd64,RBX); in foo()
/external/llvm/test/CodeGen/X86/
Dghc-cc64.ll8 @r1 = external global i64 ; assigned to register: RBX
Dabi-isel.ll9209 ; LINUX-64-PIC: pushq [[RBX:%r.x]]
9210 ; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
9211 ; LINUX-64-PIC-NEXT: callq *([[RBX]])
9212 ; LINUX-64-PIC-NEXT: callq *([[RBX]])
9213 ; LINUX-64-PIC-NEXT: popq [[RBX:%r.x]]
9247 ; DARWIN-64-STATIC: pushq [[RBX:%r.x]]
9248 ; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
9249 ; DARWIN-64-STATIC-NEXT: callq *([[RBX]])
9250 ; DARWIN-64-STATIC-NEXT: callq *([[RBX]])
9251 ; DARWIN-64-STATIC-NEXT: popq [[RBX:%r.x]]
[all …]
Ddynamic-allocas-VLAs.ll141 ; FIXME: RA has already reserved RBX, so we can't do dynamic realignment.
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-amd64-linux.c356 SC2(rbx,RBX); in synth_ucontext()
/external/valgrind/main/memcheck/
Dmc_machine.c560 if (o == GOF(RBX) && is1248) return o; in get_otrack_shadow_offset_wrk()
599 if (o == 1+ GOF(RBX) && szB == 1) return GOF(CC_NDEP); in get_otrack_shadow_offset_wrk()
656 if (o == 4+ GOF(RBX) && sz == 4) return GOF(RBX); in get_otrack_shadow_offset_wrk()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp219 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; in getX86RegNum()
/external/strace/
Dutil.c1424 # define arg0_offset ((long)(8*(current_personality ? RBX : RDI)))
Dprocess.c2679 { 8*RBX, "8*RBX" },
Dsyscall.c2228 {RBX,RCX,RDX,RSI,RDI,RBP} /* i386 ABI */ in syscall_enter()
/external/llvm/docs/
DTableGenFundamentals.rst183 R15B, R15D, R15W, R8, R8B, R8D, R8W, R9, R9B, R9D, R9W, RAX, RBP, RBX, RCX, RDI,
DCodeGenerator.rst1459 1 ``EBX`` ``RBX``