| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 74 RCInfo &RCI = RegClass[RC->getID()]; in compute() local
79 if (!RCI.Order) in compute()
80 RCI.Order.reset(new unsigned[NumRegs]); in compute()
97 RCI.Order[N++] = PhysReg; in compute()
99 RCI.NumRegs = N + CSRAlias.size(); in compute()
100 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
103 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); in compute()
106 if (StressRA && RCI.NumRegs > StressRA) in compute()
107 RCI.NumRegs = StressRA; in compute()
111 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
[all …]
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| D | AllocationOrder.cpp | 28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { in AllocationOrder()
55 if (!RCI.isReserved(Order[i])) in AllocationOrder()
65 ArrayRef<unsigned> O = RCI.getOrder(RC); in AllocationOrder()
72 !RC->contains(Hint) || RCI.isReserved(Hint))) in AllocationOrder()
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| D | RegisterPressure.cpp | 174 RCI = rci; in init()
340 const RegisterClassInfo *RCI) { in collectOperands() argument
348 else if (RCI->isAllocatable(MO.getReg())) in collectOperands()
454 collectOperands(CurrPos, PhysRegOpers, VirtRegOpers, TRI, RCI); in recede()
527 collectOperands(CurrPos, PhysRegOpers, VirtRegOpers, TRI, RCI); in advance()
669 collectOperands(MI, PhysRegOpers, VirtRegOpers, TRI, RCI); in bumpUpwardPressure()
755 collectOperands(MI, PhysRegOpers, VirtRegOpers, TRI, RCI); in bumpDownwardPressure()
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| D | AllocationOrder.h | 29 const RegisterClassInfo &RCI; variable
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| D | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
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| D | PostRASchedulerList.cpp | 198 AliasAnalysis *AA, const RegisterClassInfo &RCI, in SchedulePostRATDList() argument
214 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : in SchedulePostRATDList()
216 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL)); in SchedulePostRATDList()
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| D | CriticalAntiDepBreaker.cpp | 30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : in CriticalAntiDepBreaker() argument
35 RegClassInfo(RCI), in CriticalAntiDepBreaker()
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| D | AggressiveAntiDepBreaker.cpp | 118 const RegisterClassInfo &RCI, in AggressiveAntiDepBreaker() argument
124 RegClassInfo(RCI), in AggressiveAntiDepBreaker()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 65 const RCInfo &RCI = RegClass[RC->getID()]; in get() local
66 if (Tag != RCI.Tag) in get()
68 return RCI; in get()
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| D | RegisterPressure.h | 138 const RegisterClassInfo *RCI; variable
165 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {} in RegPressureTracker()
168 MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {} in RegPressureTracker()
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| /external/llvm/lib/Target/ |
| D | TargetRegisterInfo.cpp | 178 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) in getMatchingSuperRegClass() local
179 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
182 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); in getMatchingSuperRegClass()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 717 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) in findRepresentativeClass() local
718 SuperRegRC.setBitsInMask(RCI.getMask()); in findRepresentativeClass()
2830 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint() local
2831 E = RI->regclass_end(); RCI != E; ++RCI) { in getRegForInlineAsmConstraint()
2832 const TargetRegisterClass *RC = *RCI; in getRegForInlineAsmConstraint()
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