| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 46 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
50 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
52 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
57 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
61 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
63 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
67 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
68 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
69 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 88 int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic);
142 unsigned RegNum; member
200 return Reg.RegNum; in getReg()
227 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() argument
229 Op->Reg.RegNum = RegNum; in CreateReg()
416 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum,StringRef Mnemonic) { in matchRegisterByNumber() argument
420 if (RegNum != 29) in matchRegisterByNumber()
425 if (RegNum > 31) in matchRegisterByNumber()
428 return getReg(Mips::CPURegsRegClassID,RegNum); in matchRegisterByNumber()
433 int RegNum = -1; in tryParseRegister() local
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 148 unsigned RegNum = getMipsRegisterNumbering(Reg); in printSavedRegsBitmask() local
150 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
156 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
163 unsigned RegNum = getMipsRegisterNumbering(Reg); in printSavedRegsBitmask() local
164 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
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| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| D | MBlazeAsmParser.cpp | 96 unsigned RegNum; member
147 return Reg.RegNum; in getReg()
234 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
236 Op->Reg.RegNum = RegNum; in CreateReg()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 347 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
351 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
355 int getSEHRegNum(unsigned RegNum) const;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 122 unsigned RegNum; member
124 Values(unsigned r) : RegNum(r) {} in Values()
141 return Contents.RegNum; in getReg()
144 Contents.RegNum = Val; in setReg()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeAsmPrinter.cpp | 137 unsigned RegNum = getMBlazeRegisterNumbering(Reg); in printSavedRegsBitmask() local
139 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.h | 65 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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| D | NVPTXRegisterInfo.cpp | 305 getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 70 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
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| D | X86CodeEmitter.cpp | 1456 unsigned RegNum = X86_MC::getX86RegNum(MO.getReg()) << 4; in emitInstruction() local
1458 RegNum |= 1 << 7; in emitInstruction()
1466 RegNum |= Val; in emitInstruction()
1469 emitConstant(RegNum, 1); in emitInstruction()
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| D | X86RegisterInfo.cpp | 88 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { in getCompactUnwindRegNum() argument
89 switch (getLLVMRegNum(RegNum, isEH)) { in getCompactUnwindRegNum()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 135 unsigned RegNum; member
137 Values(unsigned r) : RegNum(r) {} in Values()
154 return Contents.RegNum; in getReg()
157 Contents.RegNum = Val; in setReg()
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| D | PPCISelLowering.cpp | 1645 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs() local
1651 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC_SVR4_Custom_AlignArgRegs()
1652 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignArgRegs()
1673 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs() local
1677 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC_SVR4_Custom_AlignFPArgRegs()
1678 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
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| /external/clang/lib/Basic/ |
| D | TargetInfo.cpp | 246 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in isValidGCCRegisterName()
299 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in getNormalizedGCCRegisterName()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 346 unsigned RegNum; member
351 unsigned RegNum; member
380 unsigned RegNum; member
510 return Reg.RegNum; in getReg()
1139 .contains(VectorList.RegNum)); in isVecListDPair()
1155 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1182 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
1409 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local
1410 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1746 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
[all …]
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1180 unsigned RegNum = GetX86RegNum(MO) << 4; in EncodeInstruction() local
1182 RegNum |= 1 << 7; in EncodeInstruction()
1190 RegNum |= Val; in EncodeInstruction()
1193 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, in EncodeInstruction()
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| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 537 const unsigned RegNum; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 485 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); in MergeLDR_STR() local
491 ((isNotVFP && RegNum > PRegNum) || in MergeLDR_STR()
492 ((Count < Limit) && RegNum == PRegNum+1))) { in MergeLDR_STR()
494 PRegNum = RegNum; in MergeLDR_STR()
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| D | ARMCodeEmitter.cpp | 1400 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); in emitLoadStoreMultipleInstruction() local
1402 RegNum < 16); in emitLoadStoreMultipleInstruction()
1403 Binary |= 0x1 << RegNum; in emitLoadStoreMultipleInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1239 unsigned RegNum = Registers[i]->EnumValue; in computeUberSets() local
1240 if (AllocatableRegs.count(RegNum)) in computeUberSets()
1243 UberSetIDs.join(0, RegNum); in computeUberSets()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 853 if (unsigned RegNum = MO2.getReg()) in printThumbAddrModeRROperand() local
854 O << ", " << getRegisterName(RegNum); in printThumbAddrModeRROperand()
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