| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 59 RegPressure.resize(NumRC); in ResourcePriorityQueue()
61 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
378 if ((RegPressure[RC->getID()] + in regPressureDelta()
380 (RegPressure[RC->getID()] + in regPressureDelta()
493 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
504 if (RegPressure[RC->getID()] > in scheduledNode()
506 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
507 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| D | ScheduleDAGRRList.cpp | 1609 std::vector<unsigned> RegPressure; member in __anonf3b964960211::RegReductionPQBase
1629 RegPressure.resize(NumRC); in RegReductionPQBase()
1631 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1655 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
1905 unsigned RP = RegPressure[Id]; in dumpRegPressure()
1932 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1951 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
1983 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
1998 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2045 RegPressure[RCId] += Cost; in scheduledNode()
[all …]
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| D | SelectionDAGISel.cpp | 223 if (TLI.getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /external/llvm/lib/CodeGen/ |
| D | MachineLICM.cpp | 93 SmallVector<unsigned, 8> RegPressure; member in __anoneddb9ad60111::MachineLICM
141 RegPressure.clear(); in releaseMemory()
342 RegPressure.resize(NumRC); in runOnMachineFunction()
343 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
654 BackTrace.push_back(RegPressure); in EnterScope()
797 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
825 RegPressure[RCId] += RCCost; in InitRegPressure()
830 RegPressure[RCId] += RCCost; in InitRegPressure()
832 RegPressure[RCId] -= RCCost; in InitRegPressure()
859 if (RCCost > RegPressure[RCId]) in UpdateRegPressure()
[all …]
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| D | MachineScheduler.cpp | 336 IntervalPressure RegPressure; member in __anonb1894f700311::ScheduleDAGMI
363 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure), in ScheduleDAGMI()
398 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.h | 202 IntervalPressure RegPressure; variable
234 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure), in VLIWMachineScheduler()
272 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 53 std::vector<unsigned> RegPressure; variable
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 63 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 78 setSchedulingPreference(Sched::RegPressure); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 79 setSchedulingPreference(Sched::RegPressure); in XCoreTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 811 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1055 return Sched::RegPressure; in getSchedulingPreference()
1066 return Sched::RegPressure; in getSchedulingPreference()
1074 return Sched::RegPressure; in getSchedulingPreference()
1079 return Sched::RegPressure; in getSchedulingPreference()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 479 setSchedulingPreference(Sched::RegPressure); in SPUTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 182 setSchedulingPreference(Sched::RegPressure); in X86TargetLowering()
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