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Searched refs:SUBREG_TO_REG (Results 1 – 14 of 14) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetOpcodes.h58 SUBREG_TO_REG = 9, enumerator
DTarget.td718 def SUBREG_TO_REG : Instruction {
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp218 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
DPeepholeOptimizer.cpp220 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h619 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
657 case TargetOpcode::SUBREG_TO_REG:
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp266 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
306 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
DInstrEmitter.cpp516 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
549 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
701 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
DScheduleDAGRRList.cpp1866 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
2087 Opc == TargetOpcode::SUBREG_TO_REG || in unscheduledNode()
2116 POpc == TargetOpcode::SUBREG_TO_REG) { in unscheduledNode()
2557 Opc == TargetOpcode::SUBREG_TO_REG || in canEnableCoalescing()
2930 SuccOpc == TargetOpcode::SUBREG_TO_REG) in AddPseudoTwoAddrDeps()
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td224 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1129 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1145 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1161 // we can use a SUBREG_TO_REG.
1163 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1273 (SUBREG_TO_REG
1281 (SUBREG_TO_REG
1434 (SUBREG_TO_REG
1468 (SUBREG_TO_REG
1475 (SUBREG_TO_REG
DX86InstrSSE.td422 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
424 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
428 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
432 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
436 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
564 (SUBREG_TO_REG (i32 0),
568 (SUBREG_TO_REG (i32 0),
[all …]
DX86InstrExtension.td162 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
DX86ISelLowering.cpp12417 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) in EmitVAARG64WithCustomInserter()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp237 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
282 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td304 // we can use a SUBREG_TO_REG.
306 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
1131 (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;