| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 329 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
330 assert(SubIdx && "This is not a subregister index"); in getSubRegIndexName()
331 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
414 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
416 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
849 unsigned SubIdx; variable
852 : TRI(tri), Reg(reg), SubIdx(subidx) {} in TRI()
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| D | TargetInstrInfo.h | 115 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
187 unsigned DestReg, unsigned SubIdx,
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 304 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
305 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
308 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
310 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
315 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
318 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
320 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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| D | CodeGenRegisters.cpp | 461 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
462 if (!SubIdx) in computeSecondarySubRegs()
465 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
924 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
928 FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1428 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1429 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1430 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1433 if (SuperIdx == SubIdx) in pruneUnitSets()
1443 SuperSetIDs.push_back(SubIdx); in pruneUnitSets()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 144 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
159 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
200 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
280 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
283 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
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| D | ExpandPostRAPseudos.cpp | 105 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
107 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
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| D | MachineCopyPropagation.cpp | 117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
118 if (!SubIdx) in isNopCopy()
120 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
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| D | MachineRegisterInfo.cpp | 80 if (unsigned SubIdx = I.getOperand().getSubReg()) { in recomputeRegClass() local
82 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); in recomputeRegClass()
84 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); in recomputeRegClass()
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| D | LiveDebugVariables.h | 45 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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| D | LiveDebugVariables.cpp | 251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx,
338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
718 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, in renameRegister() argument
728 Loc.substVirtReg(NewReg, SubIdx, *TRI); in renameRegister()
734 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister() argument
745 UV->renameRegister(OldReg, NewReg, SubIdx, TRI); in renameRegister()
751 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister() argument
753 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx); in renameRegister()
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| D | MachineInstr.cpp | 70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg() argument
73 if (SubIdx && getSubReg()) in substVirtReg()
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
76 if (SubIdx) in substVirtReg()
77 setSubReg(SubIdx); in substVirtReg()
1297 unsigned SubIdx, in substituteRegister() argument
1300 if (SubIdx) in substituteRegister()
1301 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1313 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
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| D | TwoAddressInstructionPass.cpp | 1451 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1454 mi->getOperand(0).setSubReg(SubIdx); in runOnMachineFunction()
1476 unsigned DstReg, unsigned SubIdx, in UpdateRegSequenceSrcs() argument
1483 MO.substVirtReg(DstReg, SubIdx, TRI); in UpdateRegSequenceSrcs()
1682 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
1707 MRI->getRegClass(SrcReg), SubIdx)) { in EliminateRegSequences()
1736 .addReg(DstReg, RegState::Define, SubIdx) in EliminateRegSequences()
1748 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
1749 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); in EliminateRegSequences()
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| D | MachineVerifier.cpp | 867 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
870 if (SubIdx) { in visitMachineOperand()
885 if (SubIdx) { in visitMachineOperand()
887 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
891 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
897 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
903 if (SubIdx) { in visitMachineOperand()
910 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| D | RegisterCoalescer.cpp | 159 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
845 unsigned SubIdx) { in updateRegDefsUses() argument
850 LDV->renameRegister(SrcReg, DstReg, SubIdx); in updateRegDefsUses()
860 if (DstInt && !Reads && SubIdx) in updateRegDefsUses()
870 if (SubIdx && MO.isDef()) in updateRegDefsUses()
876 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| D | Thumb2RegisterInfo.h | 35 unsigned DestReg, unsigned SubIdx, int Val,
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| D | Thumb1RegisterInfo.h | 41 unsigned DestReg, unsigned SubIdx, int Val,
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| D | ARMBaseRegisterInfo.h | 166 unsigned DestReg, unsigned SubIdx,
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 429 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
432 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
445 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
480 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
488 SubIdx == DefSubIdx && in EmitSubregNode()
503 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
513 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
520 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
537 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
558 MI->addOperand(MachineOperand::CreateImm(SubIdx)); in EmitSubregNode()
[all …]
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| D | InstrEmitter.h | 83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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| /external/llvm/lib/Target/ |
| D | TargetRegisterInfo.cpp | 41 if (SubIdx) { in print()
43 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
45 OS << ":sub(" << SubIdx << ')'; in print()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 169 unsigned &SubIdx) const;
188 unsigned DestReg, unsigned SubIdx,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 97 unsigned &SubIdx) const;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 335 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; in ExpandExtractElementF64() local
336 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in ExpandExtractElementF64()
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