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Searched refs:V3 (Results 1 – 25 of 52) sorted by relevance

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/external/eigen/test/
Dsmallvectors.cpp16 typedef Matrix<Scalar, 3, 1> V3; in smallVectors() typedef
24 V3 v3(x1, x2, x3); in smallVectors()
38 VERIFY_RAISES_ASSERT(V3(2, 1)) in smallVectors()
39 VERIFY_RAISES_ASSERT(V3(3, 2)) in smallVectors()
40 VERIFY_RAISES_ASSERT(V3(Scalar(3), 1)) in smallVectors()
41 VERIFY_RAISES_ASSERT(V3(3, Scalar(1))) in smallVectors()
42 VERIFY_RAISES_ASSERT(V3(Scalar(3), Scalar(1))) in smallVectors()
43 VERIFY_RAISES_ASSERT(V3(Scalar(123), Scalar(123))) in smallVectors()
/external/llvm/test/CodeGen/PowerPC/
Dvec_perf_shuffle.ll6 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32…
7 ret <4 x float> %V3
13 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >…
14 ret <4 x float> %V3
20 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >…
21 ret <4 x float> %V3
27 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; …
28 ret <4 x float> %V3
34 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; …
35 ret <4 x float> %V3
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td66 // LD Instruction Class in V2/V3/V4.
83 // LD Instruction Class in V2/V3/V4.
94 // ST Instruction Class in V2/V3 can take SLOT0 only.
96 // Definition of the instruction class CHANGED from V2/V3 to V4.
113 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
121 // ST Instruction Class in V2/V3 can take SLOT0 only.
123 // Definition of the instruction class CHANGED from V2/V3 to V4.
133 // ALU32 Instruction Class in V2/V3/V4.
144 // ALU64 Instruction Class in V2/V3.
147 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
[all …]
DHexagonSubtarget.h36 V1, V2, V3, V4, V5 enumerator
57 bool hasV3TOps () const { return HexagonArchVersion >= V3; } in hasV3TOps()
58 bool hasV3TOpsOnly () const { return HexagonArchVersion == V3; } in hasV3TOpsOnly()
DHexagonSubtarget.cpp53 HexagonArchVersion = V3; in HexagonSubtarget()
DHexagonIntrinsicsV3.td10 // This file describes the Hexagon V3 Compiler Intrinsics in TableGen format.
DHexagon.td27 def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
DHexagonRegisterInfo.cpp64 case HexagonSubtarget::V3: in getCalleeSavedRegs()
111 case HexagonSubtarget::V3: in getCalleeSavedRegClasses()
/external/llvm/test/Transforms/InstCombine/
Dapint-shl-trunc.ll7 ; CHECK: %[[V3:.*]] = icmp ne i39 %[[V2]], 0
8 ; CHECK: ret i1 %[[V3]]
19 ; CHECK: %[[V3:.*]] = icmp ne i799 %[[V2]], 0
20 ; CHECK: ret i1 %[[V3]]
/external/clang/test/CodeGenCXX/
Dvtt-layout.cpp32 class V3 {virtual void g(); }; class
34 class C2 : public virtual V3, virtual V2 { int i; };
51 class V3 {virtual void g(); }; class
53 class C2 : public virtual V3, virtual V2 { int i; };
Dvtable-layout.cpp223 struct V3 : virtual R3 { int r3; }; struct
235 virtual V3 *f();
237 V3 *E::f() { return 0;} in f()
/external/antlr/antlr-3.4/runtime/Python/
DREADME17 WARNING: Currently the runtime library for V3.1 is not compatible with
18 recognizers generated by ANTLR V3.0.x. If you are an application developer,
22 It is still undetermined, if a future release of the V3.1 runtime will be
23 compatible with V3.0.x recognizers or if future runtimes V3.2+ will be
24 compatible with V3.1 recognizers.
/external/llvm/unittests/Support/
DAlignOfTest.cpp68 struct V3 : V1 { virtual ~V3(); }; struct
70 struct V5 : V4, V3 { double z; virtual ~V5(); };
118 [AlignOf<V3>::Alignment > 0]
168 EXPECT_LE(alignOf<V1>(), alignOf<V3>()); in TEST()
250 EXPECT_EQ(alignOf<V3>(), alignOf<AlignedCharArrayUnion<V3> >()); in TEST()
315 EXPECT_EQ(sizeof(V3), sizeof(AlignedCharArrayUnion<V3>)); in TEST()
/external/llvm/test/Transforms/SimplifyCFG/
DPhiEliminate2.ll3 define i32 @test(i1 %C, i32 %V1, i32 %V2, i16 %V3) {
10 %V5 = sext i16 %V3 to i32 ; <i32> [#uses=1]
/external/eigen/test/eigen2/
Deigen2_smallvectors.cpp15 typedef Matrix<Scalar, 3, 1> V3; in smallVectors() typedef
22 V3 v3(x1, x2, x3); in smallVectors()
/external/llvm/test/Transforms/GlobalOpt/
D2008-04-26-SROA-Global-Align.ll28 %V3 = load double* getelementptr (%T* @G, i32 0, i32 2), align 16
30 %R2 = fadd double %R, %V3
/external/clang/test/Misc/
Ddiag-template-diffing.cpp92 int V1, V2, V3; variable
97 set3(I3<&V3, &V2>()); in test3()
/external/llvm/test/Transforms/BBVectorize/
Dmem-op-depth.ll12 %V3= load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 2), align 8
17 store float %V3, float* getelementptr inbounds ([1024 x float]* @B, i64 0, i64 2), align 8
/external/clang/test/CXX/dcl.dcl/dcl.spec/dcl.constexpr/
Dp1.cpp48 constexpr enum E3 { V3 } e3 = V3; enumerator
/external/llvm/lib/Analysis/
DLint.cpp142 const Value *V3 = 0, const Value *V4 = 0) { in CheckFailed() argument
146 WriteValue(V3); in CheckFailed()
168 #define Assert3(C, M, V1, V2, V3) \ argument
169 do { if (!(C)) { CheckFailed(M, V1, V2, V3); return; } } while (0)
170 #define Assert4(C, M, V1, V2, V3, V4) \ argument
171 do { if (!(C)) { CheckFailed(M, V1, V2, V3, V4); return; } } while (0)
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h34 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; in getPPCRegisterNumbering()
/external/antlr/antlr-3.4/runtime/Delphi/
DNOTICE.TXT3 This software contains code derived from the ANTLR V3 Java Runtime Library
/external/antlr/antlr-3.4/runtime/CSharp2/
DNOTICE.TXT3 This software contains code derived from the ANTLR V3 Java Runtime Library
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1480 SDValue V2, SDValue V3) { in QuadSRegs() argument
1489 V2, SubReg2, V3, SubReg3 }; in QuadSRegs()
1496 SDValue V2, SDValue V3) { in QuadDRegs() argument
1504 V2, SubReg2, V3, SubReg3 }; in QuadDRegs()
1511 SDValue V2, SDValue V3) { in QuadQRegs() argument
1519 V2, SubReg2, V3, SubReg3 }; in QuadQRegs()
1788 SDValue V3 = (NumVecs == 3) in SelectVST() local
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/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td47 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
105 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,

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