Searched refs:VECTOR_SHUFFLE (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 291 VECTOR_SHUFFLE, enumerator
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| D | SelectionDAGNodes.h | 1120 : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
1148 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
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| /external/llvm/test/CodeGen/ARM/ |
| D | vext.ll | 126 ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 197 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
495 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
1300 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
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| D | SelectionDAG.cpp | 488 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
1383 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); in getVectorShuffle()
3231 case ISD::VECTOR_SHUFFLE: in getNode()
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| D | DAGCombiner.cpp | 1158 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
2370 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && in SimplifyBinOpWithSameOpcodeHands()
7729 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE in visitEXTRACT_VECTOR_ELT()
8028 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) in visitBUILD_VECTOR()
8286 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && in visitVECTOR_SHUFFLE()
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| D | LegalizeDAG.cpp | 2842 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
3649 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
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| D | LegalizeIntegerTypes.cpp | 82 case ISD::VECTOR_SHUFFLE: in PromoteIntegerResult()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrFragmentsSIMD.td | 127 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
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| D | X86ISelLowering.cpp | 729 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
835 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); in X86TargetLowering()
889 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in X86TargetLowering()
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in X86TargetLowering()
1147 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1218 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in X86TargetLowering()
5059 case ISD::VECTOR_SHUFFLE: { in LowerVectorBroadcast()
5842 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { in LowerVECTOR_SHUFFLEv8i16()
5866 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { in LowerVECTOR_SHUFFLEv8i16()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
368 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
4678 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 449 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SPUTargetLowering()
2836 case ISD::VECTOR_SHUFFLE: in LowerOperation()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 461 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
552 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in ARMTargetLowering()
5250 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
8979 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
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