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Searched refs:getOpcode (Results 1 – 25 of 389) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonNewValueJump.cpp113 if (II->getOpcode() == TargetOpcode::KILL) in canBeFeederToNewValueJump()
163 if (MII->getOpcode() == Hexagon::CALLv3) in commonChecksToProhibitNewValueJump()
177 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
178 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
179 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
186 if (MII->getOpcode() == Hexagon::TFR_condset_rr || in commonChecksToProhibitNewValueJump()
187 MII->getOpcode() == Hexagon::TFR_condset_ii || in commonChecksToProhibitNewValueJump()
188 MII->getOpcode() == Hexagon::TFR_condset_ri || in commonChecksToProhibitNewValueJump()
189 MII->getOpcode() == Hexagon::TFR_condset_ir || in commonChecksToProhibitNewValueJump()
190 MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
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DHexagonRegisterInfo.cpp125 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
127 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) { in eliminateCallFramePseudoInstr()
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex()
183 if ( (MI.getOpcode() == Hexagon::LDriw) || in eliminateFrameIndex()
184 (MI.getOpcode() == Hexagon::LDrid) || in eliminateFrameIndex()
185 (MI.getOpcode() == Hexagon::LDrih) || in eliminateFrameIndex()
186 (MI.getOpcode() == Hexagon::LDriuh) || in eliminateFrameIndex()
187 (MI.getOpcode() == Hexagon::LDrib) || in eliminateFrameIndex()
188 (MI.getOpcode() == Hexagon::LDriub) || in eliminateFrameIndex()
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DHexagonSplitTFRCondSets.cpp85 switch(MI->getOpcode()) { in runOnMachineFunction()
93 if (MI->getOpcode() == Hexagon::TFR_condset_rr || in runOnMachineFunction()
94 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { in runOnMachineFunction()
98 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { in runOnMachineFunction()
129 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) { in runOnMachineFunction()
134 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) { in runOnMachineFunction()
150 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) { in runOnMachineFunction()
155 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) { in runOnMachineFunction()
178 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) { in runOnMachineFunction()
187 } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f ) { in runOnMachineFunction()
DHexagonISelDAGToDAG.cpp304 if (Const32->getOpcode() == HexagonISD::CONST32 && in SelectBaseOffsetLoad()
677 if ((Const32->getOpcode() == HexagonISD::CONST32) && in SelectBaseOffsetStore()
680 if (Base.getOpcode() == ISD::TargetGlobalAddress) { in SelectBaseOffsetStore()
754 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
761 } else if (MulOp0.getOpcode() == ISD::LOAD) { in SelectMul()
780 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
787 } else if (MulOp1.getOpcode() == ISD::LOAD) { in SelectMul()
819 if (N0.getOpcode() == ISD::SETCC) { in SelectSelect()
821 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) { in SelectSelect()
903 if (Shift.getOpcode() != ISD::SRL) { in SelectTruncate()
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/external/llvm/include/llvm/
DOperator.h43 unsigned getOpcode() const { in getOpcode() function
45 return I->getOpcode(); in getOpcode()
46 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
52 static unsigned getOpcode(const Value *V) { in getOpcode() function
54 return I->getOpcode(); in getOpcode()
56 return CE->getOpcode(); in getOpcode()
108 return I->getOpcode() == Instruction::Add || in classof()
109 I->getOpcode() == Instruction::Sub || in classof()
110 I->getOpcode() == Instruction::Mul || in classof()
111 I->getOpcode() == Instruction::Shl; in classof()
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DInstruction.h82 unsigned getOpcode() const { return getValueID() - InstructionVal; } in getOpcode() function
84 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); } in getOpcodeName()
85 bool isTerminator() const { return isTerminator(getOpcode()); } in isTerminator()
86 bool isBinaryOp() const { return isBinaryOp(getOpcode()); } in isBinaryOp()
87 bool isShift() { return isShift(getOpcode()); } in isShift()
88 bool isCast() const { return isCast(getOpcode()); } in isCast()
108 return getOpcode() == Shl || getOpcode() == LShr; in isLogicalShift()
113 return getOpcode() == AShr; in isArithmeticShift()
205 bool isAssociative() const { return isAssociative(getOpcode()); } in isAssociative()
215 bool isCommutative() const { return isCommutative(getOpcode()); } in isCommutative()
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/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp80 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
81 Addr.getOpcode() == ISD::TargetGlobalAddress) in SelectADDRri()
84 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
115 if (Addr.getOpcode() == ISD::FrameIndex) return false; in SelectADDRrr()
116 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRrr()
117 Addr.getOpcode() == ISD::TargetGlobalAddress) in SelectADDRrr()
120 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRrr()
124 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || in SelectADDRrr()
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DFPMover.cpp90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || in runOnMachineBasicBlock()
91 MI->getOpcode() == SP::FpNEGD) { in runOnMachineBasicBlock()
95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) { in runOnMachineBasicBlock()
106 if (MI->getOpcode() == SP::FpMOVD) in runOnMachineBasicBlock()
108 else if (MI->getOpcode() == SP::FpNEGD) in runOnMachineBasicBlock()
110 else if (MI->getOpcode() == SP::FpABSD) in runOnMachineBasicBlock()
/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h140 inline unsigned getOpcode() const;
363 unsigned getOpcode() const { return (unsigned short)NodeType; }
774 inline unsigned SDValue::getOpcode() const {
775 return Node->getOpcode();
970 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
978 return N->getOpcode() == ISD::LOAD ||
979 N->getOpcode() == ISD::STORE ||
980 N->getOpcode() == ISD::PREFETCH ||
981 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
982 N->getOpcode() == ISD::ATOMIC_SWAP ||
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DMachineInstr.h258 int getOpcode() const { return MCID->Opcode; }
597 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
598 getOpcode() == TargetOpcode::EH_LABEL ||
599 getOpcode() == TargetOpcode::GC_LABEL;
603 return getOpcode() == TargetOpcode::PROLOG_LABEL;
605 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
606 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
607 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
609 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
610 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineShifts.cpp106 switch (I->getOpcode()) { in CanEvaluateShifted()
201 switch (I->getOpcode()) { in GetShiftedValue()
314 bool isLeftShift = I.getOpcode() == Instruction::Shl; in FoldShiftByConstant()
319 if (I.getOpcode() != Instruction::AShr && in FoldShiftByConstant()
337 if (I.getOpcode() != Instruction::AShr) in FoldShiftByConstant()
346 if (BO->getOpcode() == Instruction::Mul && isLeftShift) in FoldShiftByConstant()
372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); in FoldShiftByConstant()
386 if (I.getOpcode() == Instruction::Shl) in FoldShiftByConstant()
389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); in FoldShiftByConstant()
408 switch (Op0BO->getOpcode()) { in FoldShiftByConstant()
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/external/dexmaker/src/dx/java/com/android/dx/ssa/
DNormalSsaInsn.java128 public Rop getOpcode() { in getOpcode() method in NormalSsaInsn
129 return insn.getOpcode(); in getOpcode()
143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) { in getLocalAssignment()
180 return insn.getOpcode().getOpcode() == RegOps.MOVE; in isNormalMoveInsn()
186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION; in isMoveException()
218 Rop opcode = getOpcode(); in hasSideEffect()
227 switch (opcode.getOpcode()) { in hasSideEffect()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp393 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
401 switch (Op.getOpcode()) { in isNegatibleForFree()
455 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
461 switch (Op.getOpcode()) { in GetNegatedExpression()
506 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
512 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
519 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
538 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
544 if (N.getOpcode() == ISD::SELECT_CC && in isSetCCEquivalent()
545 N.getOperand(2).getOpcode() == ISD::Constant && in isSetCCEquivalent()
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/external/llvm/include/llvm/MC/
DMCInstrAnalysis.h32 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
36 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
44 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
48 return Info->get(Inst.getOpcode()).isCall(); in isCall()
52 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp58 int Opcode = MI->getOpcode(); in isLoadFromStackSlot()
80 int Opcode = MI->getOpcode(); in isStoreToStackSlot()
209 if (IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
235 unsigned SecondLastOpc = SecondLastInst->getOpcode(); in AnalyzeBranch()
241 && IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
253 if (IsBRU(SecondLastInst->getOpcode()) && in AnalyzeBranch()
254 IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
316 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) in RemoveBranch()
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DXCoreISelDAGToDAG.cpp99 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRspii()
115 if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) { in SelectADDRdpii()
120 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRdpii()
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) in SelectADDRdpii()
136 if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) { in SelectADDRcpii()
141 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRcpii()
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) in SelectADDRcpii()
157 switch (N->getOpcode()) { in Select()
242 if (Chain->getOpcode() != ISD::TokenFactor) in replaceInChain()
265 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) in SelectBRIND()
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/external/llvm/lib/Target/MBlaze/
DMBlazeISelDAGToDAG.cpp101 unsigned Opc = N->getOpcode(); in isIntS32Immediate()
122 if (N.getOpcode() == ISD::FrameIndex) return false; in SelectAddrRegReg()
123 if (N.getOpcode() == ISD::TargetExternalSymbol || in SelectAddrRegReg()
124 N.getOpcode() == ISD::TargetGlobalAddress) in SelectAddrRegReg()
128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { in SelectAddrRegReg()
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable || in SelectAddrRegReg()
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable) in SelectAddrRegReg()
153 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { in SelectAddrRegImm()
190 unsigned Opcode = Node->getOpcode(); in Select()
DMBlazeInstrInfo.cpp45 if (MI->getOpcode() == MBlaze::LWI) { in isLoadFromStackSlot()
64 if (MI->getOpcode() == MBlaze::SWI) { in isStoreToStackSlot()
137 unsigned LastOpc = LastInst->getOpcode(); in AnalyzeBranch()
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in AnalyzeBranch()
162 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) && in AnalyzeBranch()
163 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) { in AnalyzeBranch()
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in AnalyzeBranch()
173 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) && in AnalyzeBranch()
174 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) { in AnalyzeBranch()
223 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) && in RemoveBranch()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp89 switch (MI.getOpcode()) { in isCoalescableExtInstr()
102 switch (MI->getOpcode()) { in isLoadFromStackSlot()
120 switch (MI->getOpcode()) { in isStoreToStackSlot()
143 if (MI->getOpcode() != PPC::RLWIMI) in commuteInstruction()
237 if (LastInst->getOpcode() == PPC::B) { in AnalyzeBranch()
242 } else if (LastInst->getOpcode() == PPC::BCC) { in AnalyzeBranch()
250 } else if (LastInst->getOpcode() == PPC::BDNZ8 || in AnalyzeBranch()
251 LastInst->getOpcode() == PPC::BDNZ) { in AnalyzeBranch()
261 } else if (LastInst->getOpcode() == PPC::BDZ8 || in AnalyzeBranch()
262 LastInst->getOpcode() == PPC::BDZ) { in AnalyzeBranch()
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DPPCBranchSelector.cpp106 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) { in runOnMachineFunction()
143 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
154 } else if (I->getOpcode() == PPC::BDNZ) { in runOnMachineFunction()
156 } else if (I->getOpcode() == PPC::BDNZ8) { in runOnMachineFunction()
158 } else if (I->getOpcode() == PPC::BDZ) { in runOnMachineFunction()
160 } else if (I->getOpcode() == PPC::BDZ8) { in runOnMachineFunction()
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
DPlainInsn.java92 return new PlainInsn(getOpcode(), getPosition(), in withRegisterOffset()
115 Rop newRop = Rops.ropFor(getOpcode().getOpcode(), getResult(), in withSourceLiteral()
130 int opcode = getOpcode().getOpcode(); in withSourceLiteral()
152 return new PlainInsn(getOpcode(), getPosition(), in withNewRegisters()
/external/dexmaker/src/dx/java/com/android/dx/dex/code/
DRopTranslator.java192 if (insn.getOpcode().getOpcode()== RegOps.MOVE_PARAM) { in calculateParamsAreInOrder()
283 Rop lastRop = lastInsn.getOpcode(); in outputBlock()
471 if (insn.getOpcode().isCommutative() in getRegs()
531 Rop rop = insn.getOpcode(); in visitPlainInsn()
532 if (rop.getOpcode() == RegOps.MARK_LOCAL) { in visitPlainInsn()
539 if (rop.getOpcode() == RegOps.MOVE_RESULT_PSEUDO) { in visitPlainInsn()
581 Rop rop = insn.getOpcode(); in visitPlainCstInsn()
582 int ropOpcode = rop.getOpcode(); in visitPlainCstInsn()
678 if (insn.getOpcode().getOpcode() != RegOps.MOVE_RESULT_PSEUDO) { in getNextMoveResultPseudo()
689 Rop rop = insn.getOpcode(); in visitThrowingCstInsn()
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp112 if (I->getOpcode() != MSP430::JMP && in RemoveBranch()
113 I->getOpcode() != MSP430::JCC && in RemoveBranch()
114 I->getOpcode() != MSP430::Br && in RemoveBranch()
115 I->getOpcode() != MSP430::Bm) in RemoveBranch()
193 if (I->getOpcode() == MSP430::Br || in AnalyzeBranch()
194 I->getOpcode() == MSP430::Bm) in AnalyzeBranch()
198 if (I->getOpcode() == MSP430::JMP) { in AnalyzeBranch()
224 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch"); in AnalyzeBranch()
297 switch (Desc.getOpcode()) { in GetInstSizeInBytes()
313 switch (MI->getOpcode()) { in GetInstSizeInBytes()
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp139 switch (MI.getOpcode()) { in isReadSpecialReg()
184 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS) in CanTailMerge()
234 if (LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
237 } else if (LastInst->getOpcode() == NVPTX::CBranch) { in AnalyzeBranch()
256 if (SecondLastInst->getOpcode() == NVPTX::CBranch && in AnalyzeBranch()
257 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
266 if (SecondLastInst->getOpcode() == NVPTX::GOTO && in AnalyzeBranch()
267 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
283 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
293 if (I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
/external/llvm/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp321 switch (N.getOpcode()) { in SelectAFormAddr()
344 switch (Op0.getOpcode()) { in SelectAFormAddr()
401 unsigned Opc = N.getOpcode(); in DFormAddressPredicate()
420 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo) in DFormAddressPredicate()
421 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) { in DFormAddressPredicate()
425 } else if (Op1.getOpcode() == ISD::Constant in DFormAddressPredicate()
426 || Op1.getOpcode() == ISD::TargetConstant) { in DFormAddressPredicate()
430 if (Op0.getOpcode() == ISD::FrameIndex) { in DFormAddressPredicate()
446 } else if (Op0.getOpcode() == ISD::Constant in DFormAddressPredicate()
447 || Op0.getOpcode() == ISD::TargetConstant) { in DFormAddressPredicate()
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