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1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16 
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //
23 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "hexagon-nvj"
25 #include "llvm/PassSupport.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/LiveVariables.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "Hexagon.h"
41 #include "HexagonTargetMachine.h"
42 #include "HexagonRegisterInfo.h"
43 #include "HexagonSubtarget.h"
44 #include "HexagonInstrInfo.h"
45 #include "HexagonMachineFunctionInfo.h"
46 
47 #include <map>
48 
49 #include "llvm/Support/CommandLine.h"
50 using namespace llvm;
51 
52 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
53 
54 static cl::opt<int>
55 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
56   "Maximum number of predicated jumps to be converted to New Value Jump"));
57 
58 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
59     cl::ZeroOrMore, cl::init(false),
60     cl::desc("Disable New Value Jumps"));
61 
62 namespace {
63   struct HexagonNewValueJump : public MachineFunctionPass {
64     const HexagonInstrInfo    *QII;
65     const HexagonRegisterInfo *QRI;
66 
67   public:
68     static char ID;
69 
HexagonNewValueJump__anon0b9583940111::HexagonNewValueJump70     HexagonNewValueJump() : MachineFunctionPass(ID) { }
71 
getAnalysisUsage__anon0b9583940111::HexagonNewValueJump72     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
73       MachineFunctionPass::getAnalysisUsage(AU);
74     }
75 
getPassName__anon0b9583940111::HexagonNewValueJump76     const char *getPassName() const {
77       return "Hexagon NewValueJump";
78     }
79 
80     virtual bool runOnMachineFunction(MachineFunction &Fn);
81 
82   private:
83 
84   };
85 
86 } // end of anonymous namespace
87 
88 char HexagonNewValueJump::ID = 0;
89 
90 // We have identified this II could be feeder to NVJ,
91 // verify that it can be.
canBeFeederToNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,MachineBasicBlock::iterator end,MachineBasicBlock::iterator skip,MachineFunction & MF)92 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
93                                       const TargetRegisterInfo *TRI,
94                                       MachineBasicBlock::iterator II,
95                                       MachineBasicBlock::iterator end,
96                                       MachineBasicBlock::iterator skip,
97                                       MachineFunction &MF) {
98 
99   // Predicated instruction can not be feeder to NVJ.
100   if (QII->isPredicated(II))
101     return false;
102 
103   // Bail out if feederReg is a paired register (double regs in
104   // our case). One would think that we can check to see if a given
105   // register cmpReg1 or cmpReg2 is a sub register of feederReg
106   // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
107   // before the callsite of this function
108   // But we can not as it comes in the following fashion.
109   //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
110   //    %R0<def> = KILL %R0, %D0<imp-use,kill>
111   //    %P0<def> = CMPEQri %R0<kill>, 0
112   // Hence, we need to check if it's a KILL instruction.
113   if (II->getOpcode() == TargetOpcode::KILL)
114     return false;
115 
116 
117   // Make sure there there is no 'def' or 'use' of any of the uses of
118   // feeder insn between it's definition, this MI and jump, jmpInst
119   // skipping compare, cmpInst.
120   // Here's the example.
121   //    r21=memub(r22+r24<<#0)
122   //    p0 = cmp.eq(r21, #0)
123   //    r4=memub(r3+r21<<#0)
124   //    if (p0.new) jump:t .LBB29_45
125   // Without this check, it will be converted into
126   //    r4=memub(r3+r21<<#0)
127   //    r21=memub(r22+r24<<#0)
128   //    p0 = cmp.eq(r21, #0)
129   //    if (p0.new) jump:t .LBB29_45
130   // and result WAR hazards if converted to New Value Jump.
131 
132   for (unsigned i = 0; i < II->getNumOperands(); ++i) {
133     if (II->getOperand(i).isReg() &&
134         (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
135       MachineBasicBlock::iterator localII = II;
136       ++localII;
137       unsigned Reg = II->getOperand(i).getReg();
138       for (MachineBasicBlock::iterator localBegin = localII;
139                         localBegin != end; ++localBegin) {
140         if (localBegin == skip ) continue;
141         // Check for Subregisters too.
142         if (localBegin->modifiesRegister(Reg, TRI) ||
143             localBegin->readsRegister(Reg, TRI))
144           return false;
145       }
146     }
147   }
148   return true;
149 }
150 
151 // These are the common checks that need to performed
152 // to determine if
153 // 1. compare instruction can be moved before jump.
154 // 2. feeder to the compare instruction can be moved before jump.
commonChecksToProhibitNewValueJump(bool afterRA,MachineBasicBlock::iterator MII)155 static bool commonChecksToProhibitNewValueJump(bool afterRA,
156                           MachineBasicBlock::iterator MII) {
157 
158   // If store in path, bail out.
159   if (MII->getDesc().mayStore())
160     return false;
161 
162   // if call in path, bail out.
163   if (MII->getOpcode() == Hexagon::CALLv3)
164     return false;
165 
166   // if NVJ is running prior to RA, do the following checks.
167   if (!afterRA) {
168     // The following Target Opcode instructions are spurious
169     // to new value jump. If they are in the path, bail out.
170     // KILL sets kill flag on the opcode. It also sets up a
171     // single register, out of pair.
172     //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
173     //    %R0<def> = KILL %R0, %D0<imp-use,kill>
174     //    %P0<def> = CMPEQri %R0<kill>, 0
175     // PHI can be anything after RA.
176     // COPY can remateriaze things in between feeder, compare and nvj.
177     if (MII->getOpcode() == TargetOpcode::KILL ||
178         MII->getOpcode() == TargetOpcode::PHI  ||
179         MII->getOpcode() == TargetOpcode::COPY)
180       return false;
181 
182     // The following pseudo Hexagon instructions sets "use" and "def"
183     // of registers by individual passes in the backend. At this time,
184     // we don't know the scope of usage and definitions of these
185     // instructions.
186     if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
187         MII->getOpcode() == Hexagon::TFR_condset_ii ||
188         MII->getOpcode() == Hexagon::TFR_condset_ri ||
189         MII->getOpcode() == Hexagon::TFR_condset_ir ||
190         MII->getOpcode() == Hexagon::LDriw_pred     ||
191         MII->getOpcode() == Hexagon::STriw_pred)
192       return false;
193   }
194 
195   return true;
196 }
197 
canCompareBeNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,unsigned pReg,bool secondReg,bool optLocation,MachineBasicBlock::iterator end,MachineFunction & MF)198 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
199                                      const TargetRegisterInfo *TRI,
200                                      MachineBasicBlock::iterator II,
201                                      unsigned pReg,
202                                      bool secondReg,
203                                      bool optLocation,
204                                      MachineBasicBlock::iterator end,
205                                      MachineFunction &MF) {
206 
207   MachineInstr *MI = II;
208 
209   // If the second operand of the compare is an imm, make sure it's in the
210   // range specified by the arch.
211   if (!secondReg) {
212     int64_t v = MI->getOperand(2).getImm();
213     if (MI->getOpcode() == Hexagon::CMPGEri ||
214        (MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
215       --v;
216 
217     if (!(isUInt<5>(v) ||
218          ((MI->getOpcode() == Hexagon::CMPEQri ||
219            MI->getOpcode() == Hexagon::CMPGTri ||
220            MI->getOpcode() == Hexagon::CMPGEri) &&
221           (v == -1))))
222       return false;
223   }
224 
225   unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
226   cmpReg1 = MI->getOperand(1).getReg();
227 
228   if (secondReg) {
229     cmpOp2 = MI->getOperand(2).getReg();
230 
231     // Make sure that that second register is not from COPY
232     // At machine code level, we don't need this, but if we decide
233     // to move new value jump prior to RA, we would be needing this.
234     MachineRegisterInfo &MRI = MF.getRegInfo();
235     if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
236       MachineInstr *def = MRI.getVRegDef(cmpOp2);
237       if (def->getOpcode() == TargetOpcode::COPY)
238         return false;
239     }
240   }
241 
242   // Walk the instructions after the compare (predicate def) to the jump,
243   // and satisfy the following conditions.
244   ++II ;
245   for (MachineBasicBlock::iterator localII = II; localII != end;
246        ++localII) {
247 
248     // Check 1.
249     // If "common" checks fail, bail out.
250     if (!commonChecksToProhibitNewValueJump(optLocation, localII))
251       return false;
252 
253     // Check 2.
254     // If there is a def or use of predicate (result of compare), bail out.
255     if (localII->modifiesRegister(pReg, TRI) ||
256         localII->readsRegister(pReg, TRI))
257       return false;
258 
259     // Check 3.
260     // If there is a def of any of the use of the compare (operands of compare),
261     // bail out.
262     // Eg.
263     //    p0 = cmp.eq(r2, r0)
264     //    r2 = r4
265     //    if (p0.new) jump:t .LBB28_3
266     if (localII->modifiesRegister(cmpReg1, TRI) ||
267         (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
268       return false;
269   }
270   return true;
271 }
272 
273 // Given a compare operator, return a matching New Value Jump
274 // compare operator. Make sure that MI here is included in
275 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
getNewValueJumpOpcode(const MachineInstr * MI,int reg,bool secondRegNewified)276 static unsigned getNewValueJumpOpcode(const MachineInstr *MI, int reg,
277                                       bool secondRegNewified) {
278   switch (MI->getOpcode()) {
279     case Hexagon::CMPEQrr:
280       return Hexagon::JMP_EQrrPt_nv_V4;
281 
282     case Hexagon::CMPEQri: {
283       if (reg >= 0)
284         return Hexagon::JMP_EQriPt_nv_V4;
285       else
286         return Hexagon::JMP_EQriPtneg_nv_V4;
287     }
288 
289     case Hexagon::CMPLTrr:
290     case Hexagon::CMPGTrr: {
291       if (secondRegNewified)
292         return Hexagon::JMP_GTrrdnPt_nv_V4;
293       else
294         return Hexagon::JMP_GTrrPt_nv_V4;
295     }
296 
297     case Hexagon::CMPGEri: {
298       if (reg >= 1)
299         return Hexagon::JMP_GTriPt_nv_V4;
300       else
301         return Hexagon::JMP_GTriPtneg_nv_V4;
302     }
303 
304     case Hexagon::CMPGTri: {
305       if (reg >= 0)
306         return Hexagon::JMP_GTriPt_nv_V4;
307       else
308         return Hexagon::JMP_GTriPtneg_nv_V4;
309     }
310 
311     case Hexagon::CMPLTUrr:
312     case Hexagon::CMPGTUrr: {
313       if (secondRegNewified)
314         return Hexagon::JMP_GTUrrdnPt_nv_V4;
315       else
316         return Hexagon::JMP_GTUrrPt_nv_V4;
317     }
318 
319     case Hexagon::CMPGTUri:
320       return Hexagon::JMP_GTUriPt_nv_V4;
321 
322     case Hexagon::CMPGEUri: {
323       if (reg == 0)
324         return Hexagon::JMP_EQrrPt_nv_V4;
325       else
326         return Hexagon::JMP_GTUriPt_nv_V4;
327     }
328 
329     default:
330        llvm_unreachable("Could not find matching New Value Jump instruction.");
331   }
332   // return *some value* to avoid compiler warning
333   return 0;
334 }
335 
runOnMachineFunction(MachineFunction & MF)336 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
337 
338   DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
339                << "********** Function: "
340                << MF.getName() << "\n");
341 
342 #if 0
343   // for now disable this, if we move NewValueJump before register
344   // allocation we need this information.
345   LiveVariables &LVs = getAnalysis<LiveVariables>();
346 #endif
347 
348   QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
349   QRI =
350     static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
351 
352   if (!QRI->Subtarget.hasV4TOps() ||
353       DisableNewValueJumps) {
354     return false;
355   }
356 
357   int nvjCount = DbgNVJCount;
358   int nvjGenerated = 0;
359 
360   // Loop through all the bb's of the function
361   for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
362         MBBb != MBBe; ++MBBb) {
363     MachineBasicBlock* MBB = MBBb;
364 
365     DEBUG(dbgs() << "** dumping bb ** "
366                  << MBB->getNumber() << "\n");
367     DEBUG(MBB->dump());
368     DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
369     bool foundJump    = false;
370     bool foundCompare = false;
371     bool invertPredicate = false;
372     unsigned predReg = 0; // predicate reg of the jump.
373     unsigned cmpReg1 = 0;
374     int cmpOp2 = 0;
375     bool MO1IsKill = false;
376     bool MO2IsKill = false;
377     MachineBasicBlock::iterator jmpPos;
378     MachineBasicBlock::iterator cmpPos;
379     MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
380     MachineBasicBlock *jmpTarget = NULL;
381     bool afterRA = false;
382     bool isSecondOpReg = false;
383     bool isSecondOpNewified = false;
384     // Traverse the basic block - bottom up
385     for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
386              MII != E;) {
387       MachineInstr *MI = --MII;
388       if (MI->isDebugValue()) {
389         continue;
390       }
391 
392       if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
393         break;
394 
395       DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
396 
397       if (!foundJump &&
398          (MI->getOpcode() == Hexagon::JMP_c ||
399           MI->getOpcode() == Hexagon::JMP_cNot ||
400           MI->getOpcode() == Hexagon::JMP_cdnPt ||
401           MI->getOpcode() == Hexagon::JMP_cdnPnt ||
402           MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
403           MI->getOpcode() == Hexagon::JMP_cdnNotPnt)) {
404         // This is where you would insert your compare and
405         // instr that feeds compare
406         jmpPos = MII;
407         jmpInstr = MI;
408         predReg = MI->getOperand(0).getReg();
409         afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
410 
411         // If ifconverter had not messed up with the kill flags of the
412         // operands, the following check on the kill flag would suffice.
413         // if(!jmpInstr->getOperand(0).isKill()) break;
414 
415         // This predicate register is live out out of BB
416         // this would only work if we can actually use Live
417         // variable analysis on phy regs - but LLVM does not
418         // provide LV analysis on phys regs.
419         //if(LVs.isLiveOut(predReg, *MBB)) break;
420 
421         // Get all the successors of this block - which will always
422         // be 2. Check if the predicate register is live in in those
423         // successor. If yes, we can not delete the predicate -
424         // I am doing this only because LLVM does not provide LiveOut
425         // at the BB level.
426         bool predLive = false;
427         for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
428                             SIE = MBB->succ_end(); SI != SIE; ++SI) {
429           MachineBasicBlock* succMBB = *SI;
430          if (succMBB->isLiveIn(predReg)) {
431             predLive = true;
432           }
433         }
434         if (predLive)
435           break;
436 
437         jmpTarget = MI->getOperand(1).getMBB();
438         foundJump = true;
439         if (MI->getOpcode() == Hexagon::JMP_cNot ||
440             MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
441             MI->getOpcode() == Hexagon::JMP_cdnNotPnt) {
442           invertPredicate = true;
443         }
444         continue;
445       }
446 
447       // No new value jump if there is a barrier. A barrier has to be in its
448       // own packet. A barrier has zero operands. We conservatively bail out
449       // here if we see any instruction with zero operands.
450       if (foundJump && MI->getNumOperands() == 0)
451         break;
452 
453       if (foundJump &&
454          !foundCompare &&
455           MI->getOperand(0).isReg() &&
456           MI->getOperand(0).getReg() == predReg) {
457 
458         // Not all compares can be new value compare. Arch Spec: 7.6.1.1
459         if (QII->isNewValueJumpCandidate(MI)) {
460 
461           assert((MI->getDesc().isCompare()) &&
462               "Only compare instruction can be collapsed into New Value Jump");
463           isSecondOpReg = MI->getOperand(2).isReg();
464 
465           if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
466                                         afterRA, jmpPos, MF))
467             break;
468 
469           cmpInstr = MI;
470           cmpPos = MII;
471           foundCompare = true;
472 
473           // We need cmpReg1 and cmpOp2(imm or reg) while building
474           // new value jump instruction.
475           cmpReg1 = MI->getOperand(1).getReg();
476           if (MI->getOperand(1).isKill())
477             MO1IsKill = true;
478 
479           if (isSecondOpReg) {
480             cmpOp2 = MI->getOperand(2).getReg();
481             if (MI->getOperand(2).isKill())
482               MO2IsKill = true;
483           } else
484             cmpOp2 = MI->getOperand(2).getImm();
485           continue;
486         }
487       }
488 
489       if (foundCompare && foundJump) {
490 
491         // If "common" checks fail, bail out on this BB.
492         if (!commonChecksToProhibitNewValueJump(afterRA, MII))
493           break;
494 
495         bool foundFeeder = false;
496         MachineBasicBlock::iterator feederPos = MII;
497         if (MI->getOperand(0).isReg() &&
498             MI->getOperand(0).isDef() &&
499            (MI->getOperand(0).getReg() == cmpReg1 ||
500             (isSecondOpReg &&
501              MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
502 
503           unsigned feederReg = MI->getOperand(0).getReg();
504 
505           // First try to see if we can get the feeder from the first operand
506           // of the compare. If we can not, and if secondOpReg is true
507           // (second operand of the compare is also register), try that one.
508           // TODO: Try to come up with some heuristic to figure out which
509           // feeder would benefit.
510 
511           if (feederReg == cmpReg1) {
512             if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
513               if (!isSecondOpReg)
514                 break;
515               else
516                 continue;
517             } else
518               foundFeeder = true;
519           }
520 
521           if (!foundFeeder &&
522                isSecondOpReg &&
523                feederReg == (unsigned) cmpOp2)
524             if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
525               break;
526 
527           if (isSecondOpReg) {
528             // In case of CMPLT, or CMPLTU, or EQ with the second register
529             // to newify, swap the operands.
530             if (cmpInstr->getOpcode() == Hexagon::CMPLTrr  ||
531                 cmpInstr->getOpcode() == Hexagon::CMPLTUrr ||
532                 (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
533                                      feederReg == (unsigned) cmpOp2)) {
534               unsigned tmp = cmpReg1;
535               bool tmpIsKill = MO1IsKill;
536               cmpReg1 = cmpOp2;
537               MO1IsKill = MO2IsKill;
538               cmpOp2 = tmp;
539               MO2IsKill = tmpIsKill;
540             }
541 
542             // Now we have swapped the operands, all we need to check is,
543             // if the second operand (after swap) is the feeder.
544             // And if it is, make a note.
545             if (feederReg == (unsigned)cmpOp2)
546               isSecondOpNewified = true;
547           }
548 
549           // Now that we are moving feeder close the jump,
550           // make sure we are respecting the kill values of
551           // the operands of the feeder.
552 
553           bool updatedIsKill = false;
554           for (unsigned i = 0; i < MI->getNumOperands(); i++) {
555             MachineOperand &MO = MI->getOperand(i);
556             if (MO.isReg() && MO.isUse()) {
557               unsigned feederReg = MO.getReg();
558               for (MachineBasicBlock::iterator localII = feederPos,
559                    end = jmpPos; localII != end; localII++) {
560                 MachineInstr *localMI = localII;
561                 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
562                   MachineOperand &localMO = localMI->getOperand(j);
563                   if (localMO.isReg() && localMO.isUse() &&
564                       localMO.isKill() && feederReg == localMO.getReg()) {
565                     // We found that there is kill of a use register
566                     // Set up a kill flag on the register
567                     localMO.setIsKill(false);
568                     MO.setIsKill();
569                     updatedIsKill = true;
570                     break;
571                   }
572                 }
573                 if (updatedIsKill) break;
574               }
575             }
576             if (updatedIsKill) break;
577           }
578 
579           MBB->splice(jmpPos, MI->getParent(), MI);
580           MBB->splice(jmpPos, MI->getParent(), cmpInstr);
581           DebugLoc dl = MI->getDebugLoc();
582           MachineInstr *NewMI;
583 
584            assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
585                       "This compare is not a New Value Jump candidate.");
586           unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
587                                                isSecondOpNewified);
588           if (invertPredicate)
589             opc = QII->getInvertedPredicatedOpcode(opc);
590 
591           // Manage the conversions from CMPGEUri to either CMPEQrr
592           // or CMPGTUri properly. See Arch spec for CMPGEUri instructions.
593           // This has to be after the getNewValueJumpOpcode function call as
594           // second operand of the compare could be modified in this logic.
595           if (cmpInstr->getOpcode() == Hexagon::CMPGEUri) {
596             if (cmpOp2 == 0) {
597               cmpOp2 = cmpReg1;
598               MO2IsKill = MO1IsKill;
599               isSecondOpReg = true;
600             } else
601               --cmpOp2;
602           }
603 
604           // Manage the conversions from CMPGEri to CMPGTUri properly.
605           // See Arch spec for CMPGEri instructions.
606           if (cmpInstr->getOpcode() == Hexagon::CMPGEri)
607             --cmpOp2;
608 
609           if (isSecondOpReg) {
610             NewMI = BuildMI(*MBB, jmpPos, dl,
611                                   QII->get(opc))
612                                     .addReg(cmpReg1, getKillRegState(MO1IsKill))
613                                     .addReg(cmpOp2, getKillRegState(MO2IsKill))
614                                     .addMBB(jmpTarget);
615           }
616           else {
617             NewMI = BuildMI(*MBB, jmpPos, dl,
618                                   QII->get(opc))
619                                     .addReg(cmpReg1, getKillRegState(MO1IsKill))
620                                     .addImm(cmpOp2)
621                                     .addMBB(jmpTarget);
622           }
623 
624           assert(NewMI && "New Value Jump Instruction Not created!");
625           if (cmpInstr->getOperand(0).isReg() &&
626               cmpInstr->getOperand(0).isKill())
627             cmpInstr->getOperand(0).setIsKill(false);
628           if (cmpInstr->getOperand(1).isReg() &&
629               cmpInstr->getOperand(1).isKill())
630             cmpInstr->getOperand(1).setIsKill(false);
631           cmpInstr->eraseFromParent();
632           jmpInstr->eraseFromParent();
633           ++nvjGenerated;
634           ++NumNVJGenerated;
635           break;
636         }
637       }
638     }
639   }
640 
641   return true;
642 
643 }
644 
createHexagonNewValueJump()645 FunctionPass *llvm::createHexagonNewValueJump() {
646   return new HexagonNewValueJump();
647 }
648