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Searched refs:getOperand (Results 1 – 25 of 390) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp37 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
42 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
43 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
44 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
45 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
54 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp57 switch (MI->getOperand(0).getImm()) { in printInst()
79 const MCOperand &Dst = MI->getOperand(0); in printInst()
80 const MCOperand &MO1 = MI->getOperand(1); in printInst()
81 const MCOperand &MO2 = MI->getOperand(2); in printInst()
82 const MCOperand &MO3 = MI->getOperand(3); in printInst()
99 const MCOperand &Dst = MI->getOperand(0); in printInst()
100 const MCOperand &MO1 = MI->getOperand(1); in printInst()
101 const MCOperand &MO2 = MI->getOperand(2); in printInst()
123 MI->getOperand(0).getReg() == ARM::SP && in printInst()
135 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
116 Base = Addr.getOperand(0); in SelectADDRdpii()
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) in SelectADDRdpii()
123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRdpii()
126 Base = Addr.getOperand(0).getOperand(0); in SelectADDRdpii()
137 Base = Addr.getOperand(0); in SelectADDRcpii()
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) in SelectADDRcpii()
144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRcpii()
147 Base = Addr.getOperand(0).getOperand(0); in SelectADDRcpii()
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp38 isa<ConstantInt>(I->getOperand(2))) in CheapToScalarize()
44 (CheapToScalarize(BO->getOperand(0), isConstant) || in CheapToScalarize()
45 CheapToScalarize(BO->getOperand(1), isConstant))) in CheapToScalarize()
49 (CheapToScalarize(CI->getOperand(0), isConstant) || in CheapToScalarize()
50 CheapToScalarize(CI->getOperand(1), isConstant))) in CheapToScalarize()
71 if (!isa<ConstantInt>(III->getOperand(2))) in FindScalarElement()
73 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue(); in FindScalarElement()
78 return III->getOperand(1); in FindScalarElement()
82 return FindScalarElement(III->getOperand(0), EltNo); in FindScalarElement()
86 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements(); in FindScalarElement()
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DInstCombineShifts.cpp23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms()
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms()
92 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
95 return CanEvaluateTruncated(I->getOperand(0), Ty); in CanEvaluateShifted()
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) && in CanEvaluateShifted()
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC); in CanEvaluateShifted()
117 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
132 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
141 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
156 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
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DInstCombineAndOrXor.cpp135 Value *X = Op->getOperand(0); in OptAndOp()
259 Value *ShVal = Op->getOperand(0); in OptAndOp()
349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0; in FoldLogicalPlusAnd()
351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1)); in FoldLogicalPlusAnd()
386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold"); in FoldLogicalPlusAnd()
387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold"); in FoldLogicalPlusAnd()
505 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1))) in decomposeBitTestICmp()
507 X = I->getOperand(0); in decomposeBitTestICmp()
517 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1))) in decomposeBitTestICmp()
519 X = I->getOperand(0); in decomposeBitTestICmp()
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DInstCombineSelect.cpp32 LHS = ICI->getOperand(0); in MatchSelectPattern()
33 RHS = ICI->getOperand(1); in MatchSelectPattern()
36 if (SI->getTrueValue() == ICI->getOperand(0) && in MatchSelectPattern()
37 SI->getFalseValue() == ICI->getOperand(1)) { in MatchSelectPattern()
52 if (SI->getTrueValue() == ICI->getOperand(1) && in MatchSelectPattern()
53 SI->getFalseValue() == ICI->getOperand(0)) { in MatchSelectPattern()
130 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType()) in FoldSelectOpOp()
136 FI->getOperand(0)->getType()->getVectorNumElements()) in FoldSelectOpOp()
143 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0), in FoldSelectOpOp()
144 FI->getOperand(0), SI.getName()+".v"); in FoldSelectOpOp()
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DInstCombineCasts.cpp43 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) { in DecomposeSimpleLinearExpr()
48 return I->getOperand(0); in DecomposeSimpleLinearExpr()
55 return I->getOperand(0); in DecomposeSimpleLinearExpr()
63 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset); in DecomposeSimpleLinearExpr()
112 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset); in PromoteCastOfAllocation()
180 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned); in EvaluateInDifferentType()
181 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned); in EvaluateInDifferentType()
191 if (I->getOperand(0)->getType() == Ty) in EvaluateInDifferentType()
192 return I->getOperand(0); in EvaluateInDifferentType()
196 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty, in EvaluateInDifferentType()
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DInstCombineSimplifyDemanded.cpp33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo)); in ShrinkDemandedConstant()
159 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
160 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
167 return I->getOperand(0); in SimplifyDemandedUseBits()
170 return I->getOperand(1); in SimplifyDemandedUseBits()
181 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
182 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); in SimplifyDemandedUseBits()
189 return I->getOperand(0); in SimplifyDemandedUseBits()
192 return I->getOperand(1); in SimplifyDemandedUseBits()
198 return I->getOperand(0); in SimplifyDemandedUseBits()
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DInstCombineCompares.cpp219 !isa<ConstantInt>(GEP->getOperand(1)) || in FoldCmpLoadFromIndexedGlobal()
220 !cast<ConstantInt>(GEP->getOperand(1))->isZero() || in FoldCmpLoadFromIndexedGlobal()
221 isa<Constant>(GEP->getOperand(2))) in FoldCmpLoadFromIndexedGlobal()
231 ConstantInt *Idx = dyn_cast<ConstantInt>(GEP->getOperand(i)); in FoldCmpLoadFromIndexedGlobal()
279 Constant *CompareRHS = cast<Constant>(ICI.getOperand(1)); in FoldCmpLoadFromIndexedGlobal()
366 Value *Idx = GEP->getOperand(2); in FoldCmpLoadFromIndexedGlobal()
488 if (ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i))) { in EvaluateGEPOffsetExpression()
509 Value *VariableIdx = GEP->getOperand(i); in EvaluateGEPOffsetExpression()
516 ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i)); in EvaluateGEPOffsetExpression()
585 RHS = BCI->getOperand(0); in FoldGEPICmp()
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/external/llvm/unittests/VMCore/
DMDBuilderTest.cpp39 Value *Op = MD1->getOperand(0); in TEST_F()
53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0))); in TEST_F()
54 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1))); in TEST_F()
55 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0)); in TEST_F()
56 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1)); in TEST_F()
67 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F()
68 EXPECT_EQ(R1->getOperand(0), R1); in TEST_F()
69 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0); in TEST_F()
70 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0); in TEST_F()
78 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F()
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitTFRCondSets.cpp89 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
90 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
91 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction()
107 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
111 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
119 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
120 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
127 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
132 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
133 addImm(MI->getOperand(3).getImm()); in runOnMachineFunction()
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DHexagonNewValueJump.cpp133 if (II->getOperand(i).isReg() && in canBeFeederToNewValueJump()
134 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in canBeFeederToNewValueJump()
137 unsigned Reg = II->getOperand(i).getReg(); in canBeFeederToNewValueJump()
212 int64_t v = MI->getOperand(2).getImm(); in canCompareBeNewValueJump()
226 cmpReg1 = MI->getOperand(1).getReg(); in canCompareBeNewValueJump()
229 cmpOp2 = MI->getOperand(2).getReg(); in canCompareBeNewValueJump()
408 predReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
437 jmpTarget = MI->getOperand(1).getMBB(); in runOnMachineFunction()
455 MI->getOperand(0).isReg() && in runOnMachineFunction()
456 MI->getOperand(0).getReg() == predReg) { in runOnMachineFunction()
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DHexagonAsmPrinter.h71 int value = MI->getOperand(OpNo).getImm(); in printImmOperand()
77 int value = MI->getOperand(OpNo).getImm(); in printNegImmOperand()
83 const MachineOperand &MO1 = MI->getOperand(OpNo); in printMEMriOperand()
84 const MachineOperand &MO2 = MI->getOperand(OpNo+1); in printMEMriOperand()
93 const MachineOperand &MO1 = MI->getOperand(OpNo); in printFrameIndexOperand()
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1); in printFrameIndexOperand()
105 if (MI->getOperand(OpNo).isImm()) { in printBranchOperand()
106 O << "$+" << MI->getOperand(OpNo).getImm()*4; in printBranchOperand()
108 printOp(MI->getOperand(OpNo), O); in printBranchOperand()
122 if (MI->getOperand(OpNo).isImm()) { in printSymbolHi()
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/external/llvm/lib/Target/CellSPU/
DSPUAsmPrinter.cpp64 const MachineOperand &MO = MI->getOperand(OpNo); in printOperand()
85 unsigned int value = MI->getOperand(OpNo).getImm(); in printU7ImmOperand()
93 char value = MI->getOperand(OpNo).getImm(); in printShufAddr()
103 O << (short) MI->getOperand(OpNo).getImm(); in printS16ImmOperand()
109 O << (unsigned short)MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
117 const MachineOperand &MO = MI->getOperand(OpNo); in printMemRegReg()
125 unsigned int value = MI->getOperand(OpNo).getImm(); in printU18ImmOperand()
133 short value = MI->getOperand(OpNo).getImm(); in printS10ImmOperand()
142 short value = MI->getOperand(OpNo).getImm(); in printU10ImmOperand()
150 assert(MI->getOperand(OpNo).isImm() && in printDFormAddr()
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp34 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
35 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
36 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
67 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
68 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
89 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
91 unsigned CCReg = MI->getOperand(OpNo+1).getReg(); in printPredicateOperand()
139 char Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
146 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU5ImmOperand()
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/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp4148 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
5197 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList()
5211 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg()
5248 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); in validateInstruction()
5264 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != in validateInstruction()
5275 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
5276 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5284 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
5285 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
5295 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp417 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
421 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
435 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
439 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
445 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, in isNegatibleForFree()
455 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
473 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, in GetNegatedExpression()
477 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
479 Op.getOperand(1)); in GetNegatedExpression()
482 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
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DLegalizeIntegerTypes.cpp155 SDValue Op = SExtPromotedInteger(N->getOperand(0)); in PromoteIntRes_AssertSext()
157 Op.getValueType(), Op, N->getOperand(1)); in PromoteIntRes_AssertSext()
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); in PromoteIntRes_AssertZext()
164 Op.getValueType(), Op, N->getOperand(1)); in PromoteIntRes_AssertZext()
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic1()
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic2()
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); in PromoteIntRes_Atomic2()
207 SDValue InOp = N->getOperand(0); in PromoteIntRes_BITCAST()
238 GetSplitVector(N->getOperand(0), Lo, Hi); in PromoteIntRes_BITCAST()
264 SDValue Op = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_BSWAP()
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/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { in SelectADDRri()
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { in SelectADDRri()
92 Base = Addr.getOperand(0); in SelectADDRri()
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
99 Base = Addr.getOperand(1); in SelectADDRri()
100 Offset = Addr.getOperand(0).getOperand(0); in SelectADDRri()
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
104 Base = Addr.getOperand(0); in SelectADDRri()
105 Offset = Addr.getOperand(1).getOperand(0); in SelectADDRri()
121 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRrr()
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/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp78 const MachineOperand &MO = OldMI.getOperand(i); in TransferImpOps()
387 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
417 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
423 MachineOperand MO = MI.getOperand(SrcOpIdx); in ExpandVLD()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp93 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr()
94 DstReg = MI.getOperand(0).getReg(); in isCoalescableExtInstr()
108 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isLoadFromStackSlot()
109 MI->getOperand(2).isFI()) { in isLoadFromStackSlot()
110 FrameIndex = MI->getOperand(2).getIndex(); in isLoadFromStackSlot()
111 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
126 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isStoreToStackSlot()
127 MI->getOperand(2).isFI()) { in isStoreToStackSlot()
128 FrameIndex = MI->getOperand(2).getIndex(); in isStoreToStackSlot()
129 return MI->getOperand(0).getReg(); in isStoreToStackSlot()
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DPPCISelDAGToDAG.cpp323 && isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
359 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) in isRotateAndMask()
392 SDValue Op0 = N->getOperand(0); in SelectBitfieldInsert()
393 SDValue Op1 = N->getOperand(1); in SelectBitfieldInsert()
413 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
414 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
415 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
416 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
423 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
424 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
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/external/llvm/lib/Target/Mips/
DMipsDirectObjLower.cpp26 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
30 Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
37 (Inst.getOperand(2)).setImm(Shift); in LowerLargeShift()
67 assert(InstIn.getOperand(2).isImm()); in LowerDextDins()
68 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDextDins()
69 assert(InstIn.getOperand(3).isImm()); in LowerDextDins()
70 int64_t size = InstIn.getOperand(3).getImm(); in LowerDextDins()
76 InstIn.getOperand(2).setImm(pos - 32); in LowerDextDins()
82 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
236 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
242 unsigned SoImm = MI.getOperand(Op).getImm(); in getSOImmOpValue()
258 unsigned SoImm = MI.getOperand(Op).getImm(); in getT2SOImmOpValue()
283 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
436 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
465 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
501 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
513 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
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