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Searched refs:getRegClass (Results 1 – 25 of 65) sorted by relevance

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/external/llvm/lib/Target/
DTargetInstrInfo.cpp34 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo
49 return TRI->getRegClass(RegClass); in getRegClass()
DTargetRegisterInfo.cpp83 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); in getAllocatableClass()
152 return TRI->getRegClass(I + CountTrailingZeros_32(Common)); in firstCommonClass()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp158 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
263 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
357 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def)) in optimizeBitcastInstr()
DRegAllocBase.cpp101 << MRI->getRegClass(VirtReg->reg)->getName() in allocatePhysRegs()
122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
DVirtRegMap.cpp94 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot()
115 << MRI->getRegClass(Reg)->getName() << "\n"; in print()
123 << "] " << MRI->getRegClass(Reg)->getName() << "\n"; in print()
DAllocationOrder.cpp29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); in AllocationOrder()
DRegisterCoalescer.cpp253 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); in setRegisters()
256 } else if (!MRI.getRegClass(Src)->contains(Dst)) { in setRegisters()
261 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters()
262 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters()
620 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) in removeCopyByCommutingDef()
730 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef()
732 if (MRI->getRegClass(DstReg) != RC) in reMaterializeTrivialDef()
1591 << MRI->getRegClass(Reg)->getName() << '\n'); in runOnMachineFunction()
DMachineSink.cpp136 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
137 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
508 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) in FindSuccToSinkTo()
DMachineRegisterInfo.cpp53 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
68 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom()
377 << MRI.getRegClass(LI.reg)->getName() << '\n'); in calculateRegClassAndHint()
DTwoAddressInstructionPass.cpp1118 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF)); in TryInstructionTransform()
1226 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1310 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB)); in processTiedPairs()
1564 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, in CoalesceExtSubRegs()
1571 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, in CoalesceExtSubRegs()
1706 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), in EliminateRegSequences()
1707 MRI->getRegClass(SrcReg), SubIdx)) { in EliminateRegSequences()
DRegisterPressure.cpp105 MRI->getRegClass(Regs[I]), TRI); in increaseVirtRegPressure()
111 decreaseSetPressure(CurrSetPressure, MRI->getRegClass(Regs[I]), TRI); in decreaseVirtRegPressure()
406 P.increase(MRI->getRegClass(Reg), TRI); in discoverVirtLiveIn()
418 P.increase(MRI->getRegClass(Reg), TRI); in discoverVirtLiveOut()
DTailDuplication.cpp285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) { in TailDuplicateAndUpdate()
396 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in ProcessPHI()
433 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in DuplicateInstruction()
443 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg)); in DuplicateInstruction()
DOptimizePHIs.cpp168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
DInlineSpiller.cpp726 MRI.getRegClass(SVI.SpillReg), &TRI); in hoistSpill()
1081 MRI.getRegClass(NewLI.reg), &TRI); in insertReload()
1099 MRI.getRegClass(NewLI.reg), &TRI); in insertSpill()
1228 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); in spillAll()
1279 << MRI.getRegClass(edit.getReg())->getName() in spill()
DCalcSpillWeights.cpp79 const TargetRegisterClass *rc = mri.getRegClass(reg); in copyHint()
DSpiller.cpp88 const TargetRegisterClass *trc = mri->getRegClass(li->reg); in trivialSpillEverywhere()
DUnreachableBlockElim.cpp201 MRI.constrainRegClass(Input, MRI.getRegClass(Output)); in runOnMachineFunction()
DMachineLICM.cpp782 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in getRegisterClassIDAndCost()
1264 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); in ExtractHoistableLoad()
1358 OrigRCs.push_back(MRI->getRegClass(DupReg)); in EliminateCSE()
1360 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) { in EliminateCSE()
DCriticalAntiDepBreaker.cpp193 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); in PrescanInstruction()
288 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); in ScanInstruction()
DRegAllocGreedy.cpp555 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
556 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
971 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1238 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1289 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg))) in tryInstructionSplit()
DMachineCSE.cpp141 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) in INITIALIZE_PASS_DEPENDENCY()
523 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg); in ProcessBlock()
DTargetInstrInfoImpl.cpp269 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); in canFoldCopy()
274 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
161 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
219 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
237 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
316 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); in AddRegisterOperand()
431 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
489 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
540 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
581 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
598 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
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/external/llvm/utils/TableGen/
DCodeGenTarget.h125 return *getRegBank().getRegClass(R); in getRegisterClass()

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