| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 86 let isPredicated = 1 in
93 let isPredicated = 1 in
100 let isPredicated = 1 in
107 let isPredicated = 1 in
114 let isPredicated = 1 in
121 let isPredicated = 1 in
128 let isPredicated = 1 in
135 let isPredicated = 1 in
144 let isPredicated = 1 in
151 let isPredicated = 1 in
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| D | HexagonInstrInfo.td | 352 let neverHasSideEffects = 1, isPredicated = 1 in
358 let neverHasSideEffects = 1, isPredicated = 1 in
364 let neverHasSideEffects = 1, isPredicated = 1 in
370 let neverHasSideEffects = 1, isPredicated = 1 in
376 let neverHasSideEffects = 1, isPredicated = 1 in
382 let neverHasSideEffects = 1, isPredicated = 1 in
388 let neverHasSideEffects = 1, isPredicated = 1 in
394 let neverHasSideEffects = 1, isPredicated = 1 in
403 let neverHasSideEffects = 1, isPredicated = 1 in
409 let neverHasSideEffects = 1, isPredicated = 1 in
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| D | HexagonInstrInfoV5.td | 41 let isPredicated = 1 in
532 let AddedComplexity = 100, isPredicated = 1 in
542 let AddedComplexity = 100, isPredicated = 1 in
554 let AddedComplexity = 100, isPredicated = 1 in
562 let AddedComplexity = 100, isPredicated = 1 in
570 let AddedComplexity = 100, isPredicated = 1 in
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| D | HexagonInstrInfo.h | 125 virtual bool isPredicated(const MachineInstr *MI) const;
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| D | HexagonPeephole.cpp | 223 if (QII->isPredicated(MI)) { in runOnMachineFunction()
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| D | HexagonInstrFormats.td | 56 bits<1> isPredicated = 0;
57 let TSFlags{6} = isPredicated;
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| D | HexagonNewValueJump.cpp | 100 if (QII->isPredicated(II)) in canBeFeederToNewValueJump()
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| D | HexagonVLIWPacketizer.cpp | 2842 if (QII->isPredicated(PacketMI)) { in CanPromoteToNewValueStore()
2843 if (!QII->isPredicated(MI)) in CanPromoteToNewValueStore()
3058 if(!QII->isPredicated(*VIN)) continue; in RestrictingDepExistInPacket()
3421 else if (QII->isPredicated(I) && in isLegalToPacketizeTogether()
3422 QII->isPredicated(J) && in isLegalToPacketizeTogether()
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| D | HexagonInstrInfo.cpp | 142 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, in InsertBranch()
2291 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in HexagonInstrInfo
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| /external/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 181 TII->isPredicated(MI); in PrescanInstruction()
234 if (!TII->isPredicated(MI)) { in ScanInstruction()
571 TII->isPredicated(MI)) in BreakAntiDependencies()
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| D | IfConversion.cpp | 665 bool isPredicated = TII->isPredicated(I); in ScanInstructions() local
669 if (!isPredicated) { in ScanInstructions()
686 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1444 if (I->isDebugValue() || TII->isPredicated(I)) in PredicateBlock()
1501 if (!TII->isPredicated(I) && !MI->isDebugValue()) { in CopyAndPredicateBlock()
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| D | RegisterScavenging.cpp | 145 bool isPred = TII->isPredicated(MI); in forward()
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| D | AggressiveAntiDepBreaker.cpp | 385 TII->isPredicated(MI)) { in PrescanInstruction()
452 TII->isPredicated(MI); in ScanInstruction()
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| D | TargetInstrInfoImpl.cpp | 152 return !isPredicated(MI); in isUnpredicatedTerminator()
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| D | BranchFolding.cpp | 1540 TII->isPredicated(PI)) in findHoistingInsertPosAndDeps()
1621 if (TII->isPredicated(TIB)) in HoistCommonCodeInSuccs()
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| D | MachineVerifier.cpp | 553 !TII->isPredicated(getBundleStart(&MBB->back()))) { in visitMachineBasicBlockBefore()
692 if (MI->isTerminator() && !TII->isPredicated(MI)) { in visitMachineBundleBefore()
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| D | MachineBasicBlock.cpp | 609 return empty() || !back().isBarrier() || TII->isPredicated(&back()); in canFallThrough()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() function in ARMBaseInstrInfo
2031 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { in optimizeCompareInstr()
2038 isPredicated(PotentialAND)) in optimizeCompareInstr()
2105 if (isPredicated(MI)) in optimizeCompareInstr()
2214 assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); in optimizeCompareInstr()
3193 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI)) in getOutputLatency()
3354 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
3359 if (Subtarget.isCortexA9() && !isPredicated(MI) && in getExecutionDomain()
3413 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); in setExecutionDomain()
3431 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); in setExecutionDomain()
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| D | ARMBaseInstrInfo.h | 75 bool isPredicated(const MachineInstr *MI) const;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 166 return !isPredicated(MI); in isUnpredicatedTerminator()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 646 virtual bool isPredicated(const MachineInstr *MI) const { in isPredicated() function
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 2472 return !isPredicated(MI); in isUnpredicatedTerminator()
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