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/external/llvm/test/CodeGen/X86/
Dnarrow-shl-cst.ll5 %and = shl i32 %x, 10
6 %shl = and i32 %and, 31744
7 ret i32 %shl
14 %or = shl i32 %x, 10
15 %shl = or i32 %or, 31744
16 ret i32 %shl
23 %xor = shl i32 %x, 10
24 %shl = xor i32 %xor, 31744
25 ret i32 %shl
32 %and = shl i64 %x, 40
[all …]
Dvshift-4.ll11 %shl = shl <2 x i64> %val, %shamt
12 store <2 x i64> %shl, <2 x i64>* %dst
22 %shl = shl <2 x i64> %val, %shamt
23 store <2 x i64> %shl, <2 x i64>* %dst
32 %shl = shl <4 x i32> %val, %shamt
33 store <4 x i32> %shl, <4 x i32>* %dst
42 %shl = shl <4 x i32> %val, %shamt
43 store <4 x i32> %shl, <4 x i32>* %dst
52 %shl = shl <4 x i32> %val, %shamt
53 store <4 x i32> %shl, <4 x i32>* %dst
[all …]
Dvshift-1.ll10 %shl = shl <2 x i64> %val, < i64 32, i64 32 >
11 store <2 x i64> %shl, <2 x i64>* %dst
22 %shl = shl <2 x i64> %val, %1
23 store <2 x i64> %shl, <2 x i64>* %dst
32 %shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
33 store <4 x i32> %shl, <4 x i32>* %dst
46 %shl = shl <4 x i32> %val, %3
47 store <4 x i32> %shl, <4 x i32>* %dst
55 %shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
56 store <8 x i16> %shl, <8 x i16>* %dst
[all …]
Dshl_undef.ll6 ; the successor shl(s) become shl undef, 1. This pattern then matches
7 ; shl x, 1 -> add x, x. add undef, undef doesn't guarentee the low
13 ; CHECK-NOT: shl
24 %tmp1506 = shl i32 %tmp1220, 1
31 %tmp1618 = shl i32 %tmp1676, 1
38 ; CHECK-NOT: shl
39 ; shl undef, 0 -> undef
42 %tmp2 = shl i32 undef, 0;
46 ; CHECK-NOT: shl
47 ; shl undef, x -> 0
[all …]
Dvec_shift4.ll11 %shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
12 %tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
22 %shl = shl <16 x i8> %r, %a ; <<16 x i8>> [#uses=1]
23 %tmp2 = bitcast <16 x i8> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
Drot64.ll9 %0 = shl i64 %x, %z
18 %0 = shl i64 %y, %z
29 %2 = shl i64 %x, %1
38 %2 = shl i64 %x, %1
46 %1 = shl i64 %x, 7
53 %0 = shl i64 %y, 7
62 %1 = shl i64 %x, 57
70 %1 = shl i64 %x, 57
Drot16.ll7 %0 = shl i16 %x, %z
18 %0 = shl i16 %y, %z
31 %2 = shl i16 %x, %1
42 %2 = shl i16 %x, %1
52 %1 = shl i16 %x, 5
61 %0 = shl i16 %y, 5
72 %1 = shl i16 %x, 11
82 %1 = shl i16 %x, 11
Drot32.ll7 %0 = shl i32 %x, %z
18 %0 = shl i32 %y, %z
31 %2 = shl i32 %x, %1
42 %2 = shl i32 %x, %1
52 %1 = shl i32 %x, 7
61 %0 = shl i32 %y, 7
72 %1 = shl i32 %x, 25
82 %1 = shl i32 %x, 25
Drotate.ll6 %B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1]
19 %C = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1]
25 %B = shl i32 %A, 5 ; <i32> [#uses=1]
33 %C = shl i32 %A, 27 ; <i32> [#uses=1]
40 %B = shl i16 %A, %shift.upgrd.5 ; <i16> [#uses=1]
53 %C = shl i16 %A, %shift.upgrd.8 ; <i16> [#uses=1]
59 %B = shl i16 %A, 5 ; <i16> [#uses=1]
67 %C = shl i16 %A, 11 ; <i16> [#uses=1]
73 %B = shl i8 %A, %Amt ; <i8> [#uses=1]
83 %C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
[all …]
/external/llvm/test/CodeGen/Mips/
Dmips64shift.ll6 %shl = shl i64 %a0, %a1
7 ret i64 %shl
27 %shl = shl i64 %a0, 10
28 ret i64 %shl
48 %shl = shl i64 %a0, 40
49 ret i64 %shl
71 %shl = shl i64 %a0, %sub
72 %or = or i64 %shl, %shr
79 %shl = shl i64 %a0, %a1
82 %or = or i64 %shr, %shl
[all …]
Drotate.ll6 %shl = shl i32 %a, %b
9 %or = or i32 %shr, %shl
16 %shl = shl i32 %a, 10
18 %or = or i32 %shl, %shr
27 %shl = shl i32 %a, %sub
28 %or = or i32 %shl, %shr
36 %shl = shl i32 %a, 22
37 %or = or i32 %shr, %shl
/external/llvm/test/CodeGen/CellSPU/
Dshift_ops.ll4 ; RUN: grep "shl " %t1.s | count 10
23 ; Shift left i16 via register, note that the second operand to shl is promoted
27 %A = shl i16 %arg1, %arg2
32 %A = shl i16 %arg2, %arg1
37 %A = shl i16 %arg1, %arg2
42 %A = shl i16 %arg2, %arg1
47 %A = shl i16 %arg1, %arg2
52 %A = shl i16 %arg2, %arg1
58 %A = shl i16 %arg1, 12
64 %A = shl i16 %arg1, 0
[all …]
Drotate_ops.ll22 %B = shl i32 %arg1, %tmp1 ; <i32> [#uses=1]
32 %B = shl i32 %arg1, %tmp1 ; <i32> [#uses=1]
41 %B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
50 %B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
59 %B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
69 %C = shl i32 %A, %tmp2 ; <i32> [#uses=1]
79 %C = shl i32 %A, %tmp2 ; <i32> [#uses=1]
86 %B = shl i32 %A, 5 ; <i32> [#uses=1]
95 %C = shl i32 %A, 27 ; <i32> [#uses=1]
106 %C = shl i16 %arg1, %tmp2 ; <i16> [#uses=1]
[all …]
/external/llvm/test/CodeGen/ARM/
Drev.ll8 %tmp4 = shl i32 %X15, 8
26 %tmp4 = shl i16 %tmp3, 8
51 %shl = shl nuw nsw i32 %conv, 8
52 %or = or i32 %conv2, %shl
53 %sext = shl i32 %or, 16
63 %shl = shl i32 %i, 24
64 %shr = ashr exact i32 %shl, 16
76 %and = shl i32 %x, 8
77 %shl = and i32 %and, 65280
84 %or10 = or i32 %or6, %shl
[all …]
Dfast-isel-shifter.ll3 define i32 @shl() nounwind ssp {
5 ; ARM: shl
7 %shl = shl i32 -1, 2
8 ret i32 %shl
15 %shl = shl i32 %src1, %src2
16 ret i32 %shl
/external/llvm/test/Transforms/InstCombine/
Dshift.ll8 %B = shl i32 %A, 0 ; <i32> [#uses=1]
16 %B = shl i32 0, %shift.upgrd.1 ; <i32> [#uses=1]
46 %B = shl i32 %A, 32 ;; shift all bits out
68 %B = shl i32 %A, 1 ;; convert to an mul instruction
78 %C = shl i32 %B, 1 ;; convert to an mul instruction
94 %B = shl i8 %A, 5 ; <i8> [#uses=1]
95 %C = shl i8 %B, 3 ; <i8> [#uses=1]
104 %B = shl i8 %A, 7 ; <i8> [#uses=1]
111 ;; The shl may be valuable to scalar evolution.
117 %C = shl i8 %B, 7 ; <i8> [#uses=1]
[all …]
Dapint-shift.ll8 %B = shl i47 %A, 0 ; <i47> [#uses=1]
16 %B = shl i41 0, %A ; <i41> [#uses=1]
45 %B = shl i32 %A, 32 ; <i32> [#uses=1]
52 %B = shl i55 %A, 1 ; <i55> [#uses=1]
61 %C = shl i55 %B, 1 ; <i55> [#uses=1]
76 %B = shl i7 %A, 4 ; <i7> [#uses=1]
77 %C = shl i7 %B, 3 ; <i7> [#uses=1]
84 %B = shl i17 %A, 16 ; <i17> [#uses=1]
93 %C = shl i19 %B, 18 ; <i19> [#uses=1]
98 ; Don't hide the shl from scalar evolution. DAGCombine will get it.
[all …]
D2010-11-01-lshr-mask.ll8 ; CHECK: %tmp3163 = shl i8 %tmp3162, 6
10 ; CHECK-NOT: shl
15 %tmp4114 = shl i8 %tmp3163, 6
29 %tmp = shl i8 %arg, 7
39 %tmp11 = shl i8 %tmp10, 5
42 ; CHECK: %tmp11 = shl nuw nsw i8 %tmp10, 5
Dbswap.ll11 %tmp7 = shl i32 %i, 8 ; <i32> [#uses=1]
14 %tmp11 = shl i32 %i, 24 ; <i32> [#uses=1]
20 %tmp2 = shl i32 %arg, 24 ; <i32> [#uses=1]
21 %tmp4 = shl i32 %arg, 8 ; <i32> [#uses=1]
34 %tmp4 = shl i16 %s, 8 ; <i16> [#uses=1]
41 %tmp4 = shl i16 %s, 8 ; <i16> [#uses=1]
52 %tmp5 = shl i32 %tmp4, 8 ; <i32> [#uses=1]
63 %tmp = shl i32 %x, 16 ; <i32> [#uses=1]
69 %tmp5 = shl i32 %tmp4, 8 ; <i32> [#uses=1]
/external/openssl/crypto/sha/asm/
Dsha512-586.pl149 &shl ("esi",14); # lo<<14
151 &shl ("edi",14); # hi<<14
158 &shl ("esi",18-14); # lo<<18
160 &shl ("edi",18-14); # hi<<18
167 &shl ("esi",23-18); # lo<<23
169 &shl ("edi",23-18); # hi<<23
214 &shl ("esi",4); # lo<<4
216 &shl ("edi",4); # hi<<4
223 &shl ("esi",25-4); # lo<<25
225 &shl ("edi",25-4); # hi<<25
[all …]
/external/llvm/test/ExecutionEngine/MCJIT/
Dtest-shift.ll6 %t1.s = shl i32 1, %shift.upgrd.1 ; <i32> [#uses=0]
7 %t2.s = shl i32 1, 4 ; <i32> [#uses=0]
9 %t1 = shl i32 1, %shift.upgrd.2 ; <i32> [#uses=0]
10 %t2 = shl i32 1, 5 ; <i32> [#uses=0]
11 %t2.s.upgrd.3 = shl i64 1, 4 ; <i64> [#uses=0]
12 %t2.upgrd.4 = shl i64 1, 5 ; <i64> [#uses=0]
22 %tr3.l = shl i64 1, 4 ; <i64> [#uses=0]
24 %tr4.l = shl i64 1, %shift.upgrd.8 ; <i64> [#uses=0]
28 %tr3.u = shl i64 1, 5 ; <i64> [#uses=0]
30 %tr4.u = shl i64 1, %shift.upgrd.10 ; <i64> [#uses=0]
/external/llvm/test/ExecutionEngine/
Dtest-shift.ll6 %t1.s = shl i32 1, %shift.upgrd.1 ; <i32> [#uses=0]
7 %t2.s = shl i32 1, 4 ; <i32> [#uses=0]
9 %t1 = shl i32 1, %shift.upgrd.2 ; <i32> [#uses=0]
10 %t2 = shl i32 1, 5 ; <i32> [#uses=0]
11 %t2.s.upgrd.3 = shl i64 1, 4 ; <i64> [#uses=0]
12 %t2.upgrd.4 = shl i64 1, 5 ; <i64> [#uses=0]
22 %tr3.l = shl i64 1, 4 ; <i64> [#uses=0]
24 %tr4.l = shl i64 1, %shift.upgrd.8 ; <i64> [#uses=0]
28 %tr3.u = shl i64 1, 5 ; <i64> [#uses=0]
30 %tr4.u = shl i64 1, %shift.upgrd.10 ; <i64> [#uses=0]
/external/llvm/test/Transforms/Reassociate/
Dshifttest.ll1 ; With shl->mul reassociation, we can see that this is (shl A, 9) * A
4 ; RUN: grep "shl .*, 9"
7 %X = shl i32 %A, 5 ; <i32> [#uses=1]
8 %Y = shl i32 %A, 4 ; <i32> [#uses=1]
/external/llvm/test/MC/Mips/
Dmips64shift.ll10 %shl = shl i64 %a0, 10
11 ret i64 %shl
31 %shl = shl i64 %a0, 40
32 ret i64 %shl
/external/llvm/test/CodeGen/MSP430/
Dshifts.ll25 %shl = shl i8 %a, %cnt
26 ret i8 %shl
49 %shl = shl i16 %a, %cnt
50 ret i16 %shl

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