| /external/llvm/lib/Target/X86/ |
| D | X86InstrXOP.td | 267 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
269 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
271 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
273 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
275 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
277 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
280 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
282 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
284 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
286 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
[all …]
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| /external/v8/src/arm/ |
| D | macro-assembler-arm.h | 336 Register src4,
341 ASSERT(!src1.is(src4));
342 ASSERT(!src2.is(src4));
343 ASSERT(!src3.is(src4));
346 if (src3.code() > src4.code()) {
349 src1.bit() | src2.bit() | src3.bit() | src4.bit(),
353 str(src4, MemOperand(sp, 4, NegPreIndex), cond);
357 Push(src3, src4, cond);
361 Push(src2, src3, src4, cond);
398 Register src4,
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 1809 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
1810 "memd($src1+$src2<<#$src3) = $src4",
1811 [(store (i64 DoubleRegs:$src4),
1819 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1820 "memd($src1<<#$src2+#$src3) = $src4",
1821 [(store (i64 DoubleRegs:$src4),
1864 DoubleRegs:$src4),
1865 "if ($src1.new) memd($src2+#$src3) = $src4",
1875 DoubleRegs:$src4),
1876 "if (!$src1.new) memd($src2+#$src3) = $src4",
[all …]
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| D | HexagonInstrInfoV5.td | 582 (f32 IntRegs:$src4)),
583 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
588 (f64 DoubleRegs:$src4)),
590 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
|
| D | HexagonInstrInfo.td | 1841 DoubleRegs:$src4),
1842 "if ($src1) memd($src2+#$src3) = $src4",
1850 DoubleRegs:$src4),
1851 "if (!$src1) memd($src2+#$src3) = $src4",
1937 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1938 "if ($src1) memb($src2+#$src3) = $src4",
1944 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1945 "if (!$src1) memb($src2+#$src3) = $src4",
2024 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2025 "if ($src1) memh($src2+#$src3) = $src4",
[all …]
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| /external/opencv/cv/src/ |
| D | cvderiv.cpp | 609 … const int *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; in icvLaplaceCol_32s16s() local
614 int s0 = src0[i] - src2[i]*2 + src4[i] + src0[i+width] + src4[i+width] + in icvLaplaceCol_32s16s()
616 int s1 = src0[i+1] - src2[i+1]*2 + src4[i+1] + src0[i+width+1] + in icvLaplaceCol_32s16s()
617 src4[i+width+1] + (src1[i+width+1] + src3[i+width+1])*4 + in icvLaplaceCol_32s16s()
624 int s0 = CV_DESCALE(src0[i] - src2[i]*2 + src4[i] + in icvLaplaceCol_32s16s()
625 src0[i+width] + src4[i+width] + in icvLaplaceCol_32s16s()
627 int s1 = CV_DESCALE(src0[i+1] - src2[i+1]*2 + src4[i+1] + in icvLaplaceCol_32s16s()
628 src0[i+width+1] + src4[i+width+1] + in icvLaplaceCol_32s16s()
751 … const float *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; in icvLaplaceCol_32f() local
754 float s0 = (src0[i] - src2[i]*2 + src4[i] + in icvLaplaceCol_32f()
[all …]
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| /external/skia/gm/ |
| D | poly2poly.cpp | 93 const int src4[] = { 0, 0, 64, 0, 64, 64, 0, 64 }; in onDraw() local
95 doDraw(canvas, &paint, src4, dst4, 4); in onDraw()
|
| /external/skia/samplecode/ |
| D | SamplePolyToPoly.cpp | 155 const int src4[] = { 0, 0, 64, 0, 64, 64, 0, 64 }; in onDrawContent() local
157 doDraw(canvas, &paint, src4, dst4, 4); in onDrawContent()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 499 GRRegs:$src4),
500 "maccu $dst1, $dst2, $src3, $src4",
505 GRRegs:$src4),
506 "maccs $dst1, $dst2, $src3, $src4",
537 GRRegs:$src4),
538 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.h | 640 void Push(Register src1, Register src2, Register src3, Register src4) { in Push() argument
645 sw(src4, MemOperand(sp, 0 * kPointerSize)); in Push()
|
| /external/skia/src/core/ |
| D | SkGeometry.cpp | 868 const float src4[] = { 0, 0, 1 }; in test_collaps_duplicates() local
880 { TEST_COLLAPS_ENTRY(src4), 2 }, in test_collaps_duplicates()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 2320 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2324 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2326 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2330 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2332 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2336 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2339 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2343 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 1212 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1215 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1253 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1256 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1878 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1879 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1898 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1899 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2186 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2188 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
[all …]
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