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Searched refs:v4i32 (Results 1 – 25 of 80) sorted by relevance

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/external/llvm/test/CodeGen/CellSPU/useful-harnesses/
Dvecoperations.c5 typedef int v4i32 __attribute__((ext_vector_type(4))); typedef
50 void print_v4i32(const char *str, v4i32 v) { in print_v4i32()
76 v4i32 v4i32_shuffle_1(v4i32 a) { in v4i32_shuffle_1()
77 v4i32 c2 = a.yzwx; in v4i32_shuffle_1()
81 v4i32 v4i32_shuffle_2(v4i32 a) { in v4i32_shuffle_2()
82 v4i32 c2 = a.zwxy; in v4i32_shuffle_2()
86 v4i32 v4i32_shuffle_3(v4i32 a) { in v4i32_shuffle_3()
87 v4i32 c2 = a.wxyz; in v4i32_shuffle_3()
91 v4i32 v4i32_shuffle_4(v4i32 a) { in v4i32_shuffle_4()
92 v4i32 c2 = a.xyzw; in v4i32_shuffle_4()
[all …]
/external/llvm/lib/Target/CellSPU/
DCellSDKIntrinsics.td43 [(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA),
49 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA),
55 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA),
61 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyui (v8i16 VECREG:$rA),
67 [(set (v4i32 VECREG:$rT), (int_spu_si_mpya (v8i16 VECREG:$rA),
74 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyh (v4i32 VECREG:$rA),
80 [(set (v4i32 VECREG:$rT), (int_spu_si_mpys (v8i16 VECREG:$rA),
86 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhh (v8i16 VECREG:$rA),
92 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhha (v8i16 VECREG:$rA),
100 [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhu (v8i16 VECREG:$rA),
[all …]
DSPUInstrInfo.td62 def v4i32: LoadDFormVec<v4i32>;
94 def v4i32: LoadAFormVec<v4i32>;
126 def v4i32: LoadXFormVec<v4i32>;
174 def v4i32: StoreDFormVec<v4i32>;
204 def v4i32: StoreAFormVec<v4i32>;
236 def v4i32: StoreXFormVec<v4i32>;
283 [(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
287 [(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
351 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
378 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
[all …]
DSPUMathInstr.td42 // v4i32, i32 multiply instruction sequence:
46 Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
48 (v4i32 (Av4i32 (v4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB)),
49 (v4i32 (MPYHv4i32 VECREG:$rB, VECREG:$rA)))),
50 (v4i32 (MPYUv4i32 VECREG:$rA, VECREG:$rB)))>;
DSPU64InstrInfo.td21 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
22 // [Note: this may be moot, since gb produces v4i32 or r32.]
67 // v2i64 seteq (equality): the setcc result is v4i32
269 def : Pat<(SPUadd64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)),
272 (v4i32 VECREG:$rCGmask)>.Fragment, R64C)>;
275 (v4i32 VECREG:$rCGmask)),
278 (v4i32 VECREG:$rCGmask)>.Fragment>;
289 def : Pat<(SPUsub64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)),
295 (v4i32 VECREG:$rCGmask)>.Fragment, R64C)>;
298 (v4i32 VECREG:$rCGmask)),
[all …]
DSPUCallingConv.td20 CCIfType<[i8,i16,i32,i64,i128,f32,f64,v16i8,v8i16,v4i32,v2i64,v4f32,v2f64],
37 v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
51 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
/external/clang/test/CodeGen/
Dmips-vector-arg.c9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) { in test_v4i32()
Dmips-vector-return.c9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) { in test_v4i32()
29 return (v4i32){0, a, 0, 0}; in test_v4i32()
Dcompound-literal.c6 typedef int v4i32 __attribute((vector_size(16)));
7 v4i32 *y = &(v4i32){1,2,3,4};
/external/llvm/test/Transforms/InstCombine/
D2012-04-23-Neon-Intrinsics.ll8 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) noun…
16 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1,…
25 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x …
33 …%b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <…
41 …%b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <…
49 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x …
53 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, …
59 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x …
67 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
68 declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td308 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
321 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
324 [(set VRRC:$vD, (and (v4i32 VRRC:$vA),
423 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
439 [(set VRRC:$vD, (vnot_ppc (or (v4i32 VRRC:$vA),
443 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
446 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
489 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>;
556 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
557 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
[all …]
DPPCCallingConv.td28 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
46 CCIfType<[v16i8, v8i16, v4i32, v4f32],
55 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
90 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
104 CCIfType<[v16i8, v8i16, v4i32, v4f32],
/external/llvm/test/CodeGen/ARM/
Dvcvt.ll108 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
116 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
124 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
132 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
136 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
137 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
138 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
139 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
Dvpadal.ll71 %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
80 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
98 %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
107 %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
120 declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
121 declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
124 declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
125 declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
Dvqdmul.ll37 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
55 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <…
81 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
133 …%1 = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; …
159 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
166 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
184 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <…
197 declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
206 …%tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %t…
[all …]
Dvpadd.ll105 %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
113 %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
129 %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
137 %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
164 declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone
165 declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone
168 declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
169 declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
Dvshll.ll15 …%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, …
39 …%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, …
65 …%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, …
78 declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
82 declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
Dneon_spill.ll25 …call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i…
43 …call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i…
47 declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwi…
Dvhadd.ll80 %tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
107 %tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
121 declare <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
125 declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
204 %tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
231 %tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
245 declare <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
249 declare <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
Dreg_sequence.ll102 …%tmp2 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp1, i32 1) ; <%struc…
105 …%tmp5 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp4, i32 1) ; <%struc…
121 tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp6, <4 x i32> %tmp7, i32 1)
133 tail call void @llvm.arm.neon.vst2.v4i32(i8* %tmp8, <4 x i32> %tmp102, <4 x i32> %tmp101, i32 1)
180 …%1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0, i32 1) ; <%struct.__ne…
184 tail call void @llvm.arm.neon.vst2.v4i32(i8* %2, <4 x i32> %tmp57, <4 x i32> %tmp60, i32 1)
185 %3 = tail call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %0, i32 1) ; <<4 x i32>> [#uses=1]
187 tail call void @llvm.arm.neon.vst1.v4i32(i8* %2, <4 x i32> %4, i32 1)
325 declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly
331 declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind
[all …]
Dvabs.ll55 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
74 declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
121 %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
131 declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone
/external/llvm/lib/Target/ARM/
DARMCallingConv.td28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
89 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
140 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
150 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
168 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
180 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMInstrNEON.td1026 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1321 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1994 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2036 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3072 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3075 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3079 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3104 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3105 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3120 v4i16, v4i32, OpNode>;
[all …]
/external/llvm/include/llvm/CodeGen/
DValueTypes.h69 v4i32 = 23, // 4 x i32 enumerator
188 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 || in is128BitVector()
246 case v4i32: in getVectorElementType()
279 case v4i32: in getVectorNumElements()
328 case v4i32: in getSizeInBits()
411 if (NumElements == 4) return MVT::v4i32; in getVectorVT()
/external/llvm/lib/Target/X86/
DX86InstrSSE.td254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
276 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
300 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
[all …]

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