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Searched refs:TII (Results 1 – 25 of 161) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp66 const HexagonInstrInfo *TII = QTM.getInstrInfo(); in runOnMachineFunction() local
87 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) { in runOnMachineFunction()
88 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) { in runOnMachineFunction()
90 TII->get(Hexagon::CONST32_Int_Real), in runOnMachineFunction()
92 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), in runOnMachineFunction()
95 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), in runOnMachineFunction()
98 TII->get(Hexagon::STriw_indexed)) in runOnMachineFunction()
102 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), in runOnMachineFunction()
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), in runOnMachineFunction()
107 TII->get(Hexagon::STriw_indexed)) in runOnMachineFunction()
[all …]
DHexagonRegisterInfo.cpp44 TII(tii) { in HexagonRegisterInfo()
167 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
168 !TII.isSpillPredRegOp(&MI)) { in eliminateFrameIndex()
174 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex()
196 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) { in eliminateFrameIndex()
198 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); in eliminateFrameIndex()
200 TII.get(Hexagon::ADD_rr), in eliminateFrameIndex()
204 TII.get(Hexagon::ADD_ri), in eliminateFrameIndex()
225 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) { in eliminateFrameIndex()
227 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset); in eliminateFrameIndex()
[all …]
DHexagonSplitTFRCondSets.cpp74 const TargetInstrInfo *TII = QTM.getInstrInfo(); in runOnMachineFunction() local
106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), in runOnMachineFunction()
110 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc2), in runOnMachineFunction()
126 TII->get(Hexagon::TFR_cPt), DestReg). in runOnMachineFunction()
131 TII->get(Hexagon::TFRI_cNotPt), DestReg). in runOnMachineFunction()
136 TII->get(Hexagon::TFRI_cNotPt_f), DestReg). in runOnMachineFunction()
152 TII->get(Hexagon::TFRI_cPt), DestReg). in runOnMachineFunction()
157 TII->get(Hexagon::TFRI_cPt_f), DestReg). in runOnMachineFunction()
166 TII->get(Hexagon::TFR_cNotPt), DestReg). in runOnMachineFunction()
182 TII->get(Hexagon::TFRI_cPt), in runOnMachineFunction()
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DHexagonFrameLowering.cpp145 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitPrologue() local
149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0); in emitPrologue()
152 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real), in emitPrologue()
154 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr), in emitPrologue()
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes); in emitPrologue()
187 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in emitEpilogue() local
196 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4)) in emitEpilogue()
199 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes); in emitEpilogue()
229 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); in spillCalleeSavedRegisters() local
260 TII.storeRegToStackSlot(MBB, MI, SuperReg, true, in spillCalleeSavedRegisters()
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DHexagonHardwareLoops.cpp58 const TargetInstrInfo *TII; member
232 TII = MF.getTarget().getInstrInfo(); in runOnMachineFunction()
489 TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg()); in convertToHardwareLoop()
494 TII->get(Hexagon::NEG), CountReg).addReg(CountReg1); in convertToHardwareLoop()
499 TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg); in convertToHardwareLoop()
505 TII->get(Hexagon::LOOP0_i)).addMBB(LoopStart).addImm(CountImm); in convertToHardwareLoop()
518 BuildMI(*LastMBB, LastI, dl, TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart); in convertToHardwareLoop()
530 TII->RemoveBranch(*LastMBB); in convertToHardwareLoop()
533 TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, dl); in convertToHardwareLoop()
626 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); in convertLoopInstr() local
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/external/llvm/lib/Target/CellSPU/
DSPUFrameLowering.cpp95 const SPUInstrInfo &TII = in emitPrologue() local
120 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel); in emitPrologue()
125 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) in emitPrologue()
129 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) in emitPrologue()
132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) in emitPrologue()
137 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) in emitPrologue()
140 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) in emitPrologue()
142 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1) in emitPrologue()
145 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) in emitPrologue()
148 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2) in emitPrologue()
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DSPUNopFiller.cpp31 const TargetInstrInfo *TII; member
37 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()), in SPUNopFiller()
96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP)); in runOnMachineBasicBlock()
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP)); in runOnMachineBasicBlock()
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP)); in runOnMachineBasicBlock()
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP)); in runOnMachineBasicBlock()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { in HandleVRSaveUpdate() argument
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
258 const PPCInstrInfo &TII = in emitPrologue() local
273 HandleVRSaveUpdate(MBBI, TII); in emitPrologue()
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DPPCBranchSelector.cpp56 const PPCInstrInfo *TII = in runOnMachineFunction() local
71 BlockSize += TII->GetInstSizeInBytes(MBBI); in runOnMachineFunction()
107 MBBStartOffset += TII->GetInstSizeInBytes(I); in runOnMachineFunction()
152 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
155 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
157 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
159 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
161 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); in runOnMachineFunction()
167 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest); in runOnMachineFunction()
DPPCRegisterInfo.cpp74 Subtarget(ST), TII(tii) { in PPCRegisterInfo()
239 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) in eliminateCallFramePseudoInstr()
244 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr()
246 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr()
249 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) in eliminateCallFramePseudoInstr()
323 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
328 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
332 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) in lowerDynamicAlloc()
336 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
345 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
[all …]
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp68 TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())), in MipsLongBranch()
88 const MipsInstrInfo *TII; member in __anon80b5238d0111::MipsLongBranch
181 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); in initMBBInfo()
220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
221 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
282 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
286 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB); in expandToLongBranch()
287 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi) in expandToLongBranch()
292 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT) in expandToLongBranch()
[all …]
DMipsSEFrameLowering.cpp36 const MipsSEInstrInfo &TII = in emitPrologue() local
56 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); in emitPrologue()
61 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); in emitPrologue()
78 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel); in emitPrologue()
110 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO); in emitPrologue()
115 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); in emitPrologue()
126 const MipsSEInstrInfo &TII = in emitEpilogue() local
143 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); in emitEpilogue()
153 TII.adjustStackPtr(SP, StackSize, MBB, MBBI); in emitEpilogue()
163 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); in spillCalleeSavedRegisters() local
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/external/llvm/lib/Target/ARM/
DThumb1FrameLowering.cpp39 const TargetInstrInfo &TII, DebugLoc dl, in emitSPUpdate() argument
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitSPUpdate()
53 const Thumb1InstrInfo &TII = in emitPrologue() local
73 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize, in emitPrologue()
78 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
135 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
146 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
167 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
211 const Thumb1InstrInfo &TII = in emitEpilogue() local
221 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); in emitEpilogue()
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DThumb1RegisterInfo.cpp78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) in emitLoadConstPool()
95 const TargetInstrInfo &TII, in emitThumbRegPlusImmInReg() argument
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
122 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) in emitThumbRegPlusImmInReg()
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
171 int NumBytes, const TargetInstrInfo &TII, in emitThumbRegPlusImmediate() argument
231 TII, MRI, MIFlags); in emitThumbRegPlusImmediate()
241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate()
247 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitThumbRegPlusImmediate()
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DARMFrameLowering.cpp94 const ARMBaseInstrInfo &TII, in isCSRestore() argument
122 DebugLoc dl, const ARMBaseInstrInfo &TII, in emitSPUpdate() argument
126 ARMCC::AL, 0, TII, MIFlags); in emitSPUpdate()
129 ARMCC::AL, 0, TII, MIFlags); in emitSPUpdate()
139 const ARMBaseInstrInfo &TII = in emitPrologue() local
162 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, in emitPrologue()
167 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
223 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) in emitPrologue()
265 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
297 TII.get(ARM::BICri), ARM::SP) in emitPrologue()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreFrameLowering.cpp48 const TargetInstrInfo &TII) { in loadFromStack() argument
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) in loadFromStack()
63 const TargetInstrInfo &TII) { in storeToStack() argument
70 BuildMI(MBB, I, dl, TII.get(Opcode)) in storeToStack()
95 const XCoreInstrInfo &TII = in emitPrologue() local
105 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); in emitPrologue()
134 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); in emitPrologue()
141 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); in emitPrologue()
155 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
160 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel); in emitPrologue()
[all …]
DXCoreRegisterInfo.cpp41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) { in XCoreRegisterInfo()
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) in eliminateCallFramePseudoInstr()
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) in eliminateCallFramePseudoInstr()
229 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in eliminateFrameIndex()
234 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) in eliminateFrameIndex()
240 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in eliminateFrameIndex()
250 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in eliminateFrameIndex()
255 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in eliminateFrameIndex()
261 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in eliminateFrameIndex()
279 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in eliminateFrameIndex()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = in emitPrologue() local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) in emitPrologue()
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW) in emitPrologue()
110 const MSP430InstrInfo &TII = in emitEpilogue() local
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW); in emitEpilogue()
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); in emitEpilogue()
161 TII.get(MSP430::SUB16ri), MSP430::SPW) in emitEpilogue()
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW) in emitEpilogue()
191 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); in spillCalleeSavedRegisters() local
[all …]
DMSP430RegisterInfo.cpp37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) { in MSP430RegisterInfo()
123 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) { in eliminateCallFramePseudoInstr()
125 TII.get(MSP430::SUB16ri), MSP430::SPW) in eliminateCallFramePseudoInstr()
128 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode()); in eliminateCallFramePseudoInstr()
134 TII.get(MSP430::ADD16ri), MSP430::SPW) in eliminateCallFramePseudoInstr()
146 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) { in eliminateCallFramePseudoInstr()
152 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri), in eliminateCallFramePseudoInstr()
201 MI.setDesc(TII.get(MSP430::MOV16rr)); in eliminateFrameIndex()
210 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) in eliminateFrameIndex()
213 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) in eliminateFrameIndex()
DMSP430BranchSelector.cpp55 const MSP430InstrInfo *TII = in runOnMachineFunction() local
70 BlockSize += TII->GetInstSizeInBytes(MBBI); in runOnMachineFunction()
107 MBBStartOffset += TII->GetInstSizeInBytes(I); in runOnMachineFunction()
154 TII->ReverseBranchCondition(Cond); in runOnMachineFunction()
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC)) in runOnMachineFunction()
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest); in runOnMachineFunction()
/external/llvm/lib/Target/Sparc/
DSparcFrameLowering.cpp32 const SparcInstrInfo &TII = in emitPrologue() local
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) in emitPrologue()
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); in emitPrologue()
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitPrologue()
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) in emitPrologue()
73 const SparcInstrInfo &TII = in emitEpilogue() local
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
/external/llvm/lib/Target/MBlaze/
DMBlazeFrameLowering.cpp225 const MBlazeInstrInfo &TII = in interruptFrameLayout() local
255 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r) in interruptFrameLayout()
263 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17) in interruptFrameLayout()
266 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18) in interruptFrameLayout()
272 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11) in interruptFrameLayout()
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11) in interruptFrameLayout()
277 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11) in interruptFrameLayout()
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR) in interruptFrameLayout()
284 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18) in interruptFrameLayout()
287 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17) in interruptFrameLayout()
[all …]
/external/llvm/lib/CodeGen/
DBranchFolding.cpp149 if (!TII->isUnpredicatedTerminator(I)) in OptimizeImpDefsBlock()
183 TII = tii; in OptimizeFunction()
200 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) in OptimizeFunction()
399 TII->ReplaceTailWithBranchTo(OldInst, NewDest); in ReplaceTailWithBranchTo()
412 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1)) in SplitMBBAt()
460 const TargetInstrInfo *TII) { in FixTail() argument
467 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { in FixTail()
470 if (!TII->ReverseBranchCondition(Cond)) { in FixTail()
471 TII->RemoveBranch(*CurMBB); in FixTail()
472 TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond, dl); in FixTail()
[all …]
DIfConversion.cpp154 const TargetInstrInfo *TII; member in __anon5a3b04910111::IfConverter
211 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, in MeetIfcvtSizeLimit()
221 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra, in MeetIfcvtSizeLimit()
265 TII = MF.getTarget().getInstrInfo(); in INITIALIZE_PASS_DEPENDENCY()
270 if (!TII) return false; in INITIALIZE_PASS_DEPENDENCY()
278 BFChange = BF.OptimizeFunction(MF, TII, in INITIALIZE_PASS_DEPENDENCY()
412 BF.OptimizeFunction(MF, TII, in INITIALIZE_PASS_DEPENDENCY()
438 if (!TII->ReverseBranchCondition(BBI.BrCond)) { in ReverseBranchCondition()
439 TII->RemoveBranch(*BBI.BB); in ReverseBranchCondition()
440 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl); in ReverseBranchCondition()
[all …]
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { in emitSPUpdate() argument
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), in emitSPUpdate()
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
638 const X86InstrInfo &TII = *TM.getInstrInfo(); in emitPrologue() local
695 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)), in emitPrologue()
740 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) in emitPrologue()
747 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) in emitPrologue()
769 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) in emitPrologue()
776 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) in emitPrologue()
[all …]

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