1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "InstPrinter/MipsInstPrinter.h"
22 #include "MCTargetDesc/MipsBaseInfo.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/CodeGen/ValueTypes.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38
39 using namespace llvm;
40
41 // If I is a shifted mask, set the size (Size) and the first bit of the
42 // mask (Pos), and return true.
43 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
IsShiftedMask(uint64_t I,uint64_t & Pos,uint64_t & Size)44 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
45 if (!isShiftedMask_64(I))
46 return false;
47
48 Size = CountPopulation_64(I);
49 Pos = CountTrailingZeros_64(I);
50 return true;
51 }
52
GetGlobalReg(SelectionDAG & DAG,EVT Ty)53 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56 }
57
getTargetNodeName(unsigned Opcode) const58 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59 switch (Opcode) {
60 case MipsISD::JmpLink: return "MipsISD::JmpLink";
61 case MipsISD::Hi: return "MipsISD::Hi";
62 case MipsISD::Lo: return "MipsISD::Lo";
63 case MipsISD::GPRel: return "MipsISD::GPRel";
64 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
65 case MipsISD::Ret: return "MipsISD::Ret";
66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
67 case MipsISD::FPCmp: return "MipsISD::FPCmp";
68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
70 case MipsISD::FPRound: return "MipsISD::FPRound";
71 case MipsISD::MAdd: return "MipsISD::MAdd";
72 case MipsISD::MAddu: return "MipsISD::MAddu";
73 case MipsISD::MSub: return "MipsISD::MSub";
74 case MipsISD::MSubu: return "MipsISD::MSubu";
75 case MipsISD::DivRem: return "MipsISD::DivRem";
76 case MipsISD::DivRemU: return "MipsISD::DivRemU";
77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
79 case MipsISD::Wrapper: return "MipsISD::Wrapper";
80 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
81 case MipsISD::Sync: return "MipsISD::Sync";
82 case MipsISD::Ext: return "MipsISD::Ext";
83 case MipsISD::Ins: return "MipsISD::Ins";
84 case MipsISD::LWL: return "MipsISD::LWL";
85 case MipsISD::LWR: return "MipsISD::LWR";
86 case MipsISD::SWL: return "MipsISD::SWL";
87 case MipsISD::SWR: return "MipsISD::SWR";
88 case MipsISD::LDL: return "MipsISD::LDL";
89 case MipsISD::LDR: return "MipsISD::LDR";
90 case MipsISD::SDL: return "MipsISD::SDL";
91 case MipsISD::SDR: return "MipsISD::SDR";
92 default: return NULL;
93 }
94 }
95
96 MipsTargetLowering::
MipsTargetLowering(MipsTargetMachine & TM)97 MipsTargetLowering(MipsTargetMachine &TM)
98 : TargetLowering(TM, new MipsTargetObjectFile()),
99 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
100 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
101 IsO32(Subtarget->isABI_O32()) {
102
103 // Mips does not have i1 type, so use i32 for
104 // setcc operations results (slt, sgt, ...).
105 setBooleanContents(ZeroOrOneBooleanContent);
106 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
107
108 // Set up the register classes
109 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
110
111 if (HasMips64)
112 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
113
114 if (Subtarget->inMips16Mode()) {
115 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
116 addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
117 }
118
119 if (!TM.Options.UseSoftFloat) {
120 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
121
122 // When dealing with single precision only, use libcalls
123 if (!Subtarget->isSingleFloat()) {
124 if (HasMips64)
125 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
126 else
127 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
128 }
129 }
130
131 // Load extented operations for i1 types must be promoted
132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
135
136 // MIPS doesn't have extending float->double load/store
137 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
138 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
139
140 // Used by legalize types to correctly generate the setcc result.
141 // Without this, every float setcc comes with a AND/OR with the result,
142 // we don't want this, since the fpcmp result goes to a flag register,
143 // which is used implicitly by brcond and select operations.
144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
145
146 // Mips Custom Operations
147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
148 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
150 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
151 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
152 setOperationAction(ISD::SELECT, MVT::f32, Custom);
153 setOperationAction(ISD::SELECT, MVT::f64, Custom);
154 setOperationAction(ISD::SELECT, MVT::i32, Custom);
155 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
156 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
157 setOperationAction(ISD::SETCC, MVT::f32, Custom);
158 setOperationAction(ISD::SETCC, MVT::f64, Custom);
159 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
160 setOperationAction(ISD::VASTART, MVT::Other, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
162 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
163 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
164 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
165 setOperationAction(ISD::LOAD, MVT::i32, Custom);
166 setOperationAction(ISD::STORE, MVT::i32, Custom);
167
168 if (!TM.Options.NoNaNsFPMath) {
169 setOperationAction(ISD::FABS, MVT::f32, Custom);
170 setOperationAction(ISD::FABS, MVT::f64, Custom);
171 }
172
173 if (HasMips64) {
174 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
175 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
176 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
177 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
178 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
179 setOperationAction(ISD::SELECT, MVT::i64, Custom);
180 setOperationAction(ISD::LOAD, MVT::i64, Custom);
181 setOperationAction(ISD::STORE, MVT::i64, Custom);
182 }
183
184 if (!HasMips64) {
185 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
186 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
187 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
188 }
189
190 setOperationAction(ISD::SDIV, MVT::i32, Expand);
191 setOperationAction(ISD::SREM, MVT::i32, Expand);
192 setOperationAction(ISD::UDIV, MVT::i32, Expand);
193 setOperationAction(ISD::UREM, MVT::i32, Expand);
194 setOperationAction(ISD::SDIV, MVT::i64, Expand);
195 setOperationAction(ISD::SREM, MVT::i64, Expand);
196 setOperationAction(ISD::UDIV, MVT::i64, Expand);
197 setOperationAction(ISD::UREM, MVT::i64, Expand);
198
199 // Operations not directly supported by Mips.
200 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
201 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
202 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
203 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
204 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
205 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
206 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
208 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
209 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
210 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
211 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
214 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
215 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::ROTL, MVT::i32, Expand);
217 setOperationAction(ISD::ROTL, MVT::i64, Expand);
218 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
219 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
220
221 if (!Subtarget->hasMips32r2())
222 setOperationAction(ISD::ROTR, MVT::i32, Expand);
223
224 if (!Subtarget->hasMips64r2())
225 setOperationAction(ISD::ROTR, MVT::i64, Expand);
226
227 setOperationAction(ISD::FSIN, MVT::f32, Expand);
228 setOperationAction(ISD::FSIN, MVT::f64, Expand);
229 setOperationAction(ISD::FCOS, MVT::f32, Expand);
230 setOperationAction(ISD::FCOS, MVT::f64, Expand);
231 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
232 setOperationAction(ISD::FPOW, MVT::f32, Expand);
233 setOperationAction(ISD::FPOW, MVT::f64, Expand);
234 setOperationAction(ISD::FLOG, MVT::f32, Expand);
235 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
236 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
237 setOperationAction(ISD::FEXP, MVT::f32, Expand);
238 setOperationAction(ISD::FMA, MVT::f32, Expand);
239 setOperationAction(ISD::FMA, MVT::f64, Expand);
240 setOperationAction(ISD::FREM, MVT::f32, Expand);
241 setOperationAction(ISD::FREM, MVT::f64, Expand);
242
243 if (!TM.Options.NoNaNsFPMath) {
244 setOperationAction(ISD::FNEG, MVT::f32, Expand);
245 setOperationAction(ISD::FNEG, MVT::f64, Expand);
246 }
247
248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
249 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
250 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
251 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
252
253 setOperationAction(ISD::VAARG, MVT::Other, Expand);
254 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
255 setOperationAction(ISD::VAEND, MVT::Other, Expand);
256
257 // Use the default for now
258 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
259 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
260
261 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
262 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
263 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
264 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
265
266 setInsertFencesForAtomic(true);
267
268 if (!Subtarget->hasSEInReg()) {
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
271 }
272
273 if (!Subtarget->hasBitCount()) {
274 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
275 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
276 }
277
278 if (!Subtarget->hasSwap()) {
279 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
280 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
281 }
282
283 if (HasMips64) {
284 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
285 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
286 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
287 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
288 }
289
290 setTargetDAGCombine(ISD::ADDE);
291 setTargetDAGCombine(ISD::SUBE);
292 setTargetDAGCombine(ISD::SDIVREM);
293 setTargetDAGCombine(ISD::UDIVREM);
294 setTargetDAGCombine(ISD::SELECT);
295 setTargetDAGCombine(ISD::AND);
296 setTargetDAGCombine(ISD::OR);
297 setTargetDAGCombine(ISD::ADD);
298
299 setMinFunctionAlignment(HasMips64 ? 3 : 2);
300
301 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
302 computeRegisterProperties();
303
304 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
305 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
306
307 maxStoresPerMemcpy = 16;
308 }
309
allowsUnalignedMemoryAccesses(EVT VT) const310 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
311 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
312
313 switch (SVT) {
314 case MVT::i64:
315 case MVT::i32:
316 return true;
317 default:
318 return false;
319 }
320 }
321
getSetCCResultType(EVT VT) const322 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
323 return MVT::i32;
324 }
325
326 // SelectMadd -
327 // Transforms a subgraph in CurDAG if the following pattern is found:
328 // (addc multLo, Lo0), (adde multHi, Hi0),
329 // where,
330 // multHi/Lo: product of multiplication
331 // Lo0: initial value of Lo register
332 // Hi0: initial value of Hi register
333 // Return true if pattern matching was successful.
SelectMadd(SDNode * ADDENode,SelectionDAG * CurDAG)334 static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
335 // ADDENode's second operand must be a flag output of an ADDC node in order
336 // for the matching to be successful.
337 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
338
339 if (ADDCNode->getOpcode() != ISD::ADDC)
340 return false;
341
342 SDValue MultHi = ADDENode->getOperand(0);
343 SDValue MultLo = ADDCNode->getOperand(0);
344 SDNode *MultNode = MultHi.getNode();
345 unsigned MultOpc = MultHi.getOpcode();
346
347 // MultHi and MultLo must be generated by the same node,
348 if (MultLo.getNode() != MultNode)
349 return false;
350
351 // and it must be a multiplication.
352 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
353 return false;
354
355 // MultLo amd MultHi must be the first and second output of MultNode
356 // respectively.
357 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
358 return false;
359
360 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
361 // of the values of MultNode, in which case MultNode will be removed in later
362 // phases.
363 // If there exist users other than ADDENode or ADDCNode, this function returns
364 // here, which will result in MultNode being mapped to a single MULT
365 // instruction node rather than a pair of MULT and MADD instructions being
366 // produced.
367 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
368 return false;
369
370 SDValue Chain = CurDAG->getEntryNode();
371 DebugLoc dl = ADDENode->getDebugLoc();
372
373 // create MipsMAdd(u) node
374 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
375
376 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
377 MultNode->getOperand(0),// Factor 0
378 MultNode->getOperand(1),// Factor 1
379 ADDCNode->getOperand(1),// Lo0
380 ADDENode->getOperand(1));// Hi0
381
382 // create CopyFromReg nodes
383 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
384 MAdd);
385 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
386 Mips::HI, MVT::i32,
387 CopyFromLo.getValue(2));
388
389 // replace uses of adde and addc here
390 if (!SDValue(ADDCNode, 0).use_empty())
391 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
392
393 if (!SDValue(ADDENode, 0).use_empty())
394 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
395
396 return true;
397 }
398
399 // SelectMsub -
400 // Transforms a subgraph in CurDAG if the following pattern is found:
401 // (addc Lo0, multLo), (sube Hi0, multHi),
402 // where,
403 // multHi/Lo: product of multiplication
404 // Lo0: initial value of Lo register
405 // Hi0: initial value of Hi register
406 // Return true if pattern matching was successful.
SelectMsub(SDNode * SUBENode,SelectionDAG * CurDAG)407 static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
408 // SUBENode's second operand must be a flag output of an SUBC node in order
409 // for the matching to be successful.
410 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
411
412 if (SUBCNode->getOpcode() != ISD::SUBC)
413 return false;
414
415 SDValue MultHi = SUBENode->getOperand(1);
416 SDValue MultLo = SUBCNode->getOperand(1);
417 SDNode *MultNode = MultHi.getNode();
418 unsigned MultOpc = MultHi.getOpcode();
419
420 // MultHi and MultLo must be generated by the same node,
421 if (MultLo.getNode() != MultNode)
422 return false;
423
424 // and it must be a multiplication.
425 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
426 return false;
427
428 // MultLo amd MultHi must be the first and second output of MultNode
429 // respectively.
430 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
431 return false;
432
433 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
434 // of the values of MultNode, in which case MultNode will be removed in later
435 // phases.
436 // If there exist users other than SUBENode or SUBCNode, this function returns
437 // here, which will result in MultNode being mapped to a single MULT
438 // instruction node rather than a pair of MULT and MSUB instructions being
439 // produced.
440 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
441 return false;
442
443 SDValue Chain = CurDAG->getEntryNode();
444 DebugLoc dl = SUBENode->getDebugLoc();
445
446 // create MipsSub(u) node
447 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
448
449 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
450 MultNode->getOperand(0),// Factor 0
451 MultNode->getOperand(1),// Factor 1
452 SUBCNode->getOperand(0),// Lo0
453 SUBENode->getOperand(0));// Hi0
454
455 // create CopyFromReg nodes
456 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
457 MSub);
458 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
459 Mips::HI, MVT::i32,
460 CopyFromLo.getValue(2));
461
462 // replace uses of sube and subc here
463 if (!SDValue(SUBCNode, 0).use_empty())
464 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
465
466 if (!SDValue(SUBENode, 0).use_empty())
467 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
468
469 return true;
470 }
471
PerformADDECombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)472 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
473 TargetLowering::DAGCombinerInfo &DCI,
474 const MipsSubtarget *Subtarget) {
475 if (DCI.isBeforeLegalize())
476 return SDValue();
477
478 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
479 SelectMadd(N, &DAG))
480 return SDValue(N, 0);
481
482 return SDValue();
483 }
484
PerformSUBECombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)485 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
486 TargetLowering::DAGCombinerInfo &DCI,
487 const MipsSubtarget *Subtarget) {
488 if (DCI.isBeforeLegalize())
489 return SDValue();
490
491 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
492 SelectMsub(N, &DAG))
493 return SDValue(N, 0);
494
495 return SDValue();
496 }
497
PerformDivRemCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)498 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
499 TargetLowering::DAGCombinerInfo &DCI,
500 const MipsSubtarget *Subtarget) {
501 if (DCI.isBeforeLegalizeOps())
502 return SDValue();
503
504 EVT Ty = N->getValueType(0);
505 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
506 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
507 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
508 MipsISD::DivRemU;
509 DebugLoc dl = N->getDebugLoc();
510
511 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
512 N->getOperand(0), N->getOperand(1));
513 SDValue InChain = DAG.getEntryNode();
514 SDValue InGlue = DivRem;
515
516 // insert MFLO
517 if (N->hasAnyUseOfValue(0)) {
518 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
519 InGlue);
520 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
521 InChain = CopyFromLo.getValue(1);
522 InGlue = CopyFromLo.getValue(2);
523 }
524
525 // insert MFHI
526 if (N->hasAnyUseOfValue(1)) {
527 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
528 HI, Ty, InGlue);
529 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
530 }
531
532 return SDValue();
533 }
534
FPCondCCodeToFCC(ISD::CondCode CC)535 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
536 switch (CC) {
537 default: llvm_unreachable("Unknown fp condition code!");
538 case ISD::SETEQ:
539 case ISD::SETOEQ: return Mips::FCOND_OEQ;
540 case ISD::SETUNE: return Mips::FCOND_UNE;
541 case ISD::SETLT:
542 case ISD::SETOLT: return Mips::FCOND_OLT;
543 case ISD::SETGT:
544 case ISD::SETOGT: return Mips::FCOND_OGT;
545 case ISD::SETLE:
546 case ISD::SETOLE: return Mips::FCOND_OLE;
547 case ISD::SETGE:
548 case ISD::SETOGE: return Mips::FCOND_OGE;
549 case ISD::SETULT: return Mips::FCOND_ULT;
550 case ISD::SETULE: return Mips::FCOND_ULE;
551 case ISD::SETUGT: return Mips::FCOND_UGT;
552 case ISD::SETUGE: return Mips::FCOND_UGE;
553 case ISD::SETUO: return Mips::FCOND_UN;
554 case ISD::SETO: return Mips::FCOND_OR;
555 case ISD::SETNE:
556 case ISD::SETONE: return Mips::FCOND_ONE;
557 case ISD::SETUEQ: return Mips::FCOND_UEQ;
558 }
559 }
560
561
562 // Returns true if condition code has to be inverted.
InvertFPCondCode(Mips::CondCode CC)563 static bool InvertFPCondCode(Mips::CondCode CC) {
564 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
565 return false;
566
567 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
568 "Illegal Condition Code");
569
570 return true;
571 }
572
573 // Creates and returns an FPCmp node from a setcc node.
574 // Returns Op if setcc is not a floating point comparison.
CreateFPCmp(SelectionDAG & DAG,const SDValue & Op)575 static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
576 // must be a SETCC node
577 if (Op.getOpcode() != ISD::SETCC)
578 return Op;
579
580 SDValue LHS = Op.getOperand(0);
581
582 if (!LHS.getValueType().isFloatingPoint())
583 return Op;
584
585 SDValue RHS = Op.getOperand(1);
586 DebugLoc dl = Op.getDebugLoc();
587
588 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
589 // node if necessary.
590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
591
592 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
593 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
594 }
595
596 // Creates and returns a CMovFPT/F node.
CreateCMovFP(SelectionDAG & DAG,SDValue Cond,SDValue True,SDValue False,DebugLoc DL)597 static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
598 SDValue False, DebugLoc DL) {
599 bool invert = InvertFPCondCode((Mips::CondCode)
600 cast<ConstantSDNode>(Cond.getOperand(2))
601 ->getSExtValue());
602
603 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
604 True.getValueType(), True, False, Cond);
605 }
606
PerformSELECTCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)607 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
608 TargetLowering::DAGCombinerInfo &DCI,
609 const MipsSubtarget *Subtarget) {
610 if (DCI.isBeforeLegalizeOps())
611 return SDValue();
612
613 SDValue SetCC = N->getOperand(0);
614
615 if ((SetCC.getOpcode() != ISD::SETCC) ||
616 !SetCC.getOperand(0).getValueType().isInteger())
617 return SDValue();
618
619 SDValue False = N->getOperand(2);
620 EVT FalseTy = False.getValueType();
621
622 if (!FalseTy.isInteger())
623 return SDValue();
624
625 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
626
627 if (!CN || CN->getZExtValue())
628 return SDValue();
629
630 const DebugLoc DL = N->getDebugLoc();
631 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
632 SDValue True = N->getOperand(1);
633
634 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
635 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
636
637 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
638 }
639
PerformANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)640 static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
641 TargetLowering::DAGCombinerInfo &DCI,
642 const MipsSubtarget *Subtarget) {
643 // Pattern match EXT.
644 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
645 // => ext $dst, $src, size, pos
646 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
647 return SDValue();
648
649 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
650 unsigned ShiftRightOpc = ShiftRight.getOpcode();
651
652 // Op's first operand must be a shift right.
653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
654 return SDValue();
655
656 // The second operand of the shift must be an immediate.
657 ConstantSDNode *CN;
658 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
659 return SDValue();
660
661 uint64_t Pos = CN->getZExtValue();
662 uint64_t SMPos, SMSize;
663
664 // Op's second operand must be a shifted mask.
665 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
666 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
667 return SDValue();
668
669 // Return if the shifted mask does not start at bit 0 or the sum of its size
670 // and Pos exceeds the word's size.
671 EVT ValTy = N->getValueType(0);
672 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
673 return SDValue();
674
675 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
676 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
677 DAG.getConstant(SMSize, MVT::i32));
678 }
679
PerformORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)680 static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
681 TargetLowering::DAGCombinerInfo &DCI,
682 const MipsSubtarget *Subtarget) {
683 // Pattern match INS.
684 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
685 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
686 // => ins $dst, $src, size, pos, $src1
687 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
688 return SDValue();
689
690 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
691 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
692 ConstantSDNode *CN;
693
694 // See if Op's first operand matches (and $src1 , mask0).
695 if (And0.getOpcode() != ISD::AND)
696 return SDValue();
697
698 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
699 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
700 return SDValue();
701
702 // See if Op's second operand matches (and (shl $src, pos), mask1).
703 if (And1.getOpcode() != ISD::AND)
704 return SDValue();
705
706 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
707 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
708 return SDValue();
709
710 // The shift masks must have the same position and size.
711 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
712 return SDValue();
713
714 SDValue Shl = And1.getOperand(0);
715 if (Shl.getOpcode() != ISD::SHL)
716 return SDValue();
717
718 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
719 return SDValue();
720
721 unsigned Shamt = CN->getZExtValue();
722
723 // Return if the shift amount and the first bit position of mask are not the
724 // same.
725 EVT ValTy = N->getValueType(0);
726 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
727 return SDValue();
728
729 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
730 DAG.getConstant(SMPos0, MVT::i32),
731 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
732 }
733
PerformADDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget * Subtarget)734 static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
735 TargetLowering::DAGCombinerInfo &DCI,
736 const MipsSubtarget *Subtarget) {
737 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
738
739 if (DCI.isBeforeLegalizeOps())
740 return SDValue();
741
742 SDValue Add = N->getOperand(1);
743
744 if (Add.getOpcode() != ISD::ADD)
745 return SDValue();
746
747 SDValue Lo = Add.getOperand(1);
748
749 if ((Lo.getOpcode() != MipsISD::Lo) ||
750 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
751 return SDValue();
752
753 EVT ValTy = N->getValueType(0);
754 DebugLoc DL = N->getDebugLoc();
755
756 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
757 Add.getOperand(0));
758 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
759 }
760
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const761 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
762 const {
763 SelectionDAG &DAG = DCI.DAG;
764 unsigned opc = N->getOpcode();
765
766 switch (opc) {
767 default: break;
768 case ISD::ADDE:
769 return PerformADDECombine(N, DAG, DCI, Subtarget);
770 case ISD::SUBE:
771 return PerformSUBECombine(N, DAG, DCI, Subtarget);
772 case ISD::SDIVREM:
773 case ISD::UDIVREM:
774 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
775 case ISD::SELECT:
776 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
777 case ISD::AND:
778 return PerformANDCombine(N, DAG, DCI, Subtarget);
779 case ISD::OR:
780 return PerformORCombine(N, DAG, DCI, Subtarget);
781 case ISD::ADD:
782 return PerformADDCombine(N, DAG, DCI, Subtarget);
783 }
784
785 return SDValue();
786 }
787
788 SDValue MipsTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const789 LowerOperation(SDValue Op, SelectionDAG &DAG) const
790 {
791 switch (Op.getOpcode())
792 {
793 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
794 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
795 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
796 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
797 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
798 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
799 case ISD::SELECT: return LowerSELECT(Op, DAG);
800 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
801 case ISD::SETCC: return LowerSETCC(Op, DAG);
802 case ISD::VASTART: return LowerVASTART(Op, DAG);
803 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
804 case ISD::FABS: return LowerFABS(Op, DAG);
805 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
806 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
807 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
808 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
809 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
810 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
811 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
812 case ISD::LOAD: return LowerLOAD(Op, DAG);
813 case ISD::STORE: return LowerSTORE(Op, DAG);
814 }
815 return SDValue();
816 }
817
818 //===----------------------------------------------------------------------===//
819 // Lower helper functions
820 //===----------------------------------------------------------------------===//
821
822 // AddLiveIn - This helper function adds the specified physical register to the
823 // MachineFunction as a live in value. It also creates a corresponding
824 // virtual register for it.
825 static unsigned
AddLiveIn(MachineFunction & MF,unsigned PReg,const TargetRegisterClass * RC)826 AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
827 {
828 assert(RC->contains(PReg) && "Not the correct regclass!");
829 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
830 MF.getRegInfo().addLiveIn(PReg, VReg);
831 return VReg;
832 }
833
834 // Get fp branch code (not opcode) from condition code.
GetFPBranchCodeFromCond(Mips::CondCode CC)835 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
836 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
837 return Mips::BRANCH_T;
838
839 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
840 "Invalid CondCode.");
841
842 return Mips::BRANCH_F;
843 }
844
845 /*
846 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
847 DebugLoc dl,
848 const MipsSubtarget *Subtarget,
849 const TargetInstrInfo *TII,
850 bool isFPCmp, unsigned Opc) {
851 // There is no need to expand CMov instructions if target has
852 // conditional moves.
853 if (Subtarget->hasCondMov())
854 return BB;
855
856 // To "insert" a SELECT_CC instruction, we actually have to insert the
857 // diamond control-flow pattern. The incoming instruction knows the
858 // destination vreg to set, the condition code register to branch on, the
859 // true/false values to select between, and a branch opcode to use.
860 const BasicBlock *LLVM_BB = BB->getBasicBlock();
861 MachineFunction::iterator It = BB;
862 ++It;
863
864 // thisMBB:
865 // ...
866 // TrueVal = ...
867 // setcc r1, r2, r3
868 // bNE r1, r0, copy1MBB
869 // fallthrough --> copy0MBB
870 MachineBasicBlock *thisMBB = BB;
871 MachineFunction *F = BB->getParent();
872 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
873 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
874 F->insert(It, copy0MBB);
875 F->insert(It, sinkMBB);
876
877 // Transfer the remainder of BB and its successor edges to sinkMBB.
878 sinkMBB->splice(sinkMBB->begin(), BB,
879 llvm::next(MachineBasicBlock::iterator(MI)),
880 BB->end());
881 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
882
883 // Next, add the true and fallthrough blocks as its successors.
884 BB->addSuccessor(copy0MBB);
885 BB->addSuccessor(sinkMBB);
886
887 // Emit the right instruction according to the type of the operands compared
888 if (isFPCmp)
889 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
890 else
891 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
892 .addReg(Mips::ZERO).addMBB(sinkMBB);
893
894 // copy0MBB:
895 // %FalseValue = ...
896 // # fallthrough to sinkMBB
897 BB = copy0MBB;
898
899 // Update machine-CFG edges
900 BB->addSuccessor(sinkMBB);
901
902 // sinkMBB:
903 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
904 // ...
905 BB = sinkMBB;
906
907 if (isFPCmp)
908 BuildMI(*BB, BB->begin(), dl,
909 TII->get(Mips::PHI), MI->getOperand(0).getReg())
910 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
911 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
912 else
913 BuildMI(*BB, BB->begin(), dl,
914 TII->get(Mips::PHI), MI->getOperand(0).getReg())
915 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
916 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
917
918 MI->eraseFromParent(); // The pseudo instruction is gone now.
919 return BB;
920 }
921 */
922 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const923 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
924 MachineBasicBlock *BB) const {
925 switch (MI->getOpcode()) {
926 default: llvm_unreachable("Unexpected instr type to insert");
927 case Mips::ATOMIC_LOAD_ADD_I8:
928 case Mips::ATOMIC_LOAD_ADD_I8_P8:
929 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
930 case Mips::ATOMIC_LOAD_ADD_I16:
931 case Mips::ATOMIC_LOAD_ADD_I16_P8:
932 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
933 case Mips::ATOMIC_LOAD_ADD_I32:
934 case Mips::ATOMIC_LOAD_ADD_I32_P8:
935 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
936 case Mips::ATOMIC_LOAD_ADD_I64:
937 case Mips::ATOMIC_LOAD_ADD_I64_P8:
938 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
939
940 case Mips::ATOMIC_LOAD_AND_I8:
941 case Mips::ATOMIC_LOAD_AND_I8_P8:
942 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
943 case Mips::ATOMIC_LOAD_AND_I16:
944 case Mips::ATOMIC_LOAD_AND_I16_P8:
945 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
946 case Mips::ATOMIC_LOAD_AND_I32:
947 case Mips::ATOMIC_LOAD_AND_I32_P8:
948 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
949 case Mips::ATOMIC_LOAD_AND_I64:
950 case Mips::ATOMIC_LOAD_AND_I64_P8:
951 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
952
953 case Mips::ATOMIC_LOAD_OR_I8:
954 case Mips::ATOMIC_LOAD_OR_I8_P8:
955 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
956 case Mips::ATOMIC_LOAD_OR_I16:
957 case Mips::ATOMIC_LOAD_OR_I16_P8:
958 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
959 case Mips::ATOMIC_LOAD_OR_I32:
960 case Mips::ATOMIC_LOAD_OR_I32_P8:
961 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
962 case Mips::ATOMIC_LOAD_OR_I64:
963 case Mips::ATOMIC_LOAD_OR_I64_P8:
964 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
965
966 case Mips::ATOMIC_LOAD_XOR_I8:
967 case Mips::ATOMIC_LOAD_XOR_I8_P8:
968 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
969 case Mips::ATOMIC_LOAD_XOR_I16:
970 case Mips::ATOMIC_LOAD_XOR_I16_P8:
971 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
972 case Mips::ATOMIC_LOAD_XOR_I32:
973 case Mips::ATOMIC_LOAD_XOR_I32_P8:
974 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
975 case Mips::ATOMIC_LOAD_XOR_I64:
976 case Mips::ATOMIC_LOAD_XOR_I64_P8:
977 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
978
979 case Mips::ATOMIC_LOAD_NAND_I8:
980 case Mips::ATOMIC_LOAD_NAND_I8_P8:
981 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
982 case Mips::ATOMIC_LOAD_NAND_I16:
983 case Mips::ATOMIC_LOAD_NAND_I16_P8:
984 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
985 case Mips::ATOMIC_LOAD_NAND_I32:
986 case Mips::ATOMIC_LOAD_NAND_I32_P8:
987 return EmitAtomicBinary(MI, BB, 4, 0, true);
988 case Mips::ATOMIC_LOAD_NAND_I64:
989 case Mips::ATOMIC_LOAD_NAND_I64_P8:
990 return EmitAtomicBinary(MI, BB, 8, 0, true);
991
992 case Mips::ATOMIC_LOAD_SUB_I8:
993 case Mips::ATOMIC_LOAD_SUB_I8_P8:
994 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
995 case Mips::ATOMIC_LOAD_SUB_I16:
996 case Mips::ATOMIC_LOAD_SUB_I16_P8:
997 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
998 case Mips::ATOMIC_LOAD_SUB_I32:
999 case Mips::ATOMIC_LOAD_SUB_I32_P8:
1000 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1001 case Mips::ATOMIC_LOAD_SUB_I64:
1002 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1003 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1004
1005 case Mips::ATOMIC_SWAP_I8:
1006 case Mips::ATOMIC_SWAP_I8_P8:
1007 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1008 case Mips::ATOMIC_SWAP_I16:
1009 case Mips::ATOMIC_SWAP_I16_P8:
1010 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1011 case Mips::ATOMIC_SWAP_I32:
1012 case Mips::ATOMIC_SWAP_I32_P8:
1013 return EmitAtomicBinary(MI, BB, 4, 0);
1014 case Mips::ATOMIC_SWAP_I64:
1015 case Mips::ATOMIC_SWAP_I64_P8:
1016 return EmitAtomicBinary(MI, BB, 8, 0);
1017
1018 case Mips::ATOMIC_CMP_SWAP_I8:
1019 case Mips::ATOMIC_CMP_SWAP_I8_P8:
1020 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1021 case Mips::ATOMIC_CMP_SWAP_I16:
1022 case Mips::ATOMIC_CMP_SWAP_I16_P8:
1023 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1024 case Mips::ATOMIC_CMP_SWAP_I32:
1025 case Mips::ATOMIC_CMP_SWAP_I32_P8:
1026 return EmitAtomicCmpSwap(MI, BB, 4);
1027 case Mips::ATOMIC_CMP_SWAP_I64:
1028 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1029 return EmitAtomicCmpSwap(MI, BB, 8);
1030 }
1031 }
1032
1033 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1034 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1035 MachineBasicBlock *
EmitAtomicBinary(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1036 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1037 unsigned Size, unsigned BinOpcode,
1038 bool Nand) const {
1039 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1040
1041 MachineFunction *MF = BB->getParent();
1042 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1043 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1044 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1045 DebugLoc dl = MI->getDebugLoc();
1046 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1047
1048 if (Size == 4) {
1049 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1050 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1051 AND = Mips::AND;
1052 NOR = Mips::NOR;
1053 ZERO = Mips::ZERO;
1054 BEQ = Mips::BEQ;
1055 }
1056 else {
1057 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1058 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1059 AND = Mips::AND64;
1060 NOR = Mips::NOR64;
1061 ZERO = Mips::ZERO_64;
1062 BEQ = Mips::BEQ64;
1063 }
1064
1065 unsigned OldVal = MI->getOperand(0).getReg();
1066 unsigned Ptr = MI->getOperand(1).getReg();
1067 unsigned Incr = MI->getOperand(2).getReg();
1068
1069 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1070 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1071 unsigned Success = RegInfo.createVirtualRegister(RC);
1072
1073 // insert new blocks after the current block
1074 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1075 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1076 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1077 MachineFunction::iterator It = BB;
1078 ++It;
1079 MF->insert(It, loopMBB);
1080 MF->insert(It, exitMBB);
1081
1082 // Transfer the remainder of BB and its successor edges to exitMBB.
1083 exitMBB->splice(exitMBB->begin(), BB,
1084 llvm::next(MachineBasicBlock::iterator(MI)),
1085 BB->end());
1086 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1087
1088 // thisMBB:
1089 // ...
1090 // fallthrough --> loopMBB
1091 BB->addSuccessor(loopMBB);
1092 loopMBB->addSuccessor(loopMBB);
1093 loopMBB->addSuccessor(exitMBB);
1094
1095 // loopMBB:
1096 // ll oldval, 0(ptr)
1097 // <binop> storeval, oldval, incr
1098 // sc success, storeval, 0(ptr)
1099 // beq success, $0, loopMBB
1100 BB = loopMBB;
1101 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1102 if (Nand) {
1103 // and andres, oldval, incr
1104 // nor storeval, $0, andres
1105 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1106 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1107 } else if (BinOpcode) {
1108 // <binop> storeval, oldval, incr
1109 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1110 } else {
1111 StoreVal = Incr;
1112 }
1113 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1114 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1115
1116 MI->eraseFromParent(); // The instruction is gone now.
1117
1118 return exitMBB;
1119 }
1120
1121 MachineBasicBlock *
EmitAtomicBinaryPartword(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1122 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1123 MachineBasicBlock *BB,
1124 unsigned Size, unsigned BinOpcode,
1125 bool Nand) const {
1126 assert((Size == 1 || Size == 2) &&
1127 "Unsupported size for EmitAtomicBinaryPartial.");
1128
1129 MachineFunction *MF = BB->getParent();
1130 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1131 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1132 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1133 DebugLoc dl = MI->getDebugLoc();
1134 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1135 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1136
1137 unsigned Dest = MI->getOperand(0).getReg();
1138 unsigned Ptr = MI->getOperand(1).getReg();
1139 unsigned Incr = MI->getOperand(2).getReg();
1140
1141 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1142 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1143 unsigned Mask = RegInfo.createVirtualRegister(RC);
1144 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1145 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1146 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1147 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1148 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1149 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1150 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1151 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1152 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1153 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1154 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1155 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1156 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1157 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1158 unsigned Success = RegInfo.createVirtualRegister(RC);
1159
1160 // insert new blocks after the current block
1161 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1162 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1163 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1164 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1165 MachineFunction::iterator It = BB;
1166 ++It;
1167 MF->insert(It, loopMBB);
1168 MF->insert(It, sinkMBB);
1169 MF->insert(It, exitMBB);
1170
1171 // Transfer the remainder of BB and its successor edges to exitMBB.
1172 exitMBB->splice(exitMBB->begin(), BB,
1173 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1174 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1175
1176 BB->addSuccessor(loopMBB);
1177 loopMBB->addSuccessor(loopMBB);
1178 loopMBB->addSuccessor(sinkMBB);
1179 sinkMBB->addSuccessor(exitMBB);
1180
1181 // thisMBB:
1182 // addiu masklsb2,$0,-4 # 0xfffffffc
1183 // and alignedaddr,ptr,masklsb2
1184 // andi ptrlsb2,ptr,3
1185 // sll shiftamt,ptrlsb2,3
1186 // ori maskupper,$0,255 # 0xff
1187 // sll mask,maskupper,shiftamt
1188 // nor mask2,$0,mask
1189 // sll incr2,incr,shiftamt
1190
1191 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1192 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1193 .addReg(Mips::ZERO).addImm(-4);
1194 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1195 .addReg(Ptr).addReg(MaskLSB2);
1196 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1197 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1198 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1199 .addReg(Mips::ZERO).addImm(MaskImm);
1200 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1201 .addReg(ShiftAmt).addReg(MaskUpper);
1202 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1203 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1204
1205 // atomic.load.binop
1206 // loopMBB:
1207 // ll oldval,0(alignedaddr)
1208 // binop binopres,oldval,incr2
1209 // and newval,binopres,mask
1210 // and maskedoldval0,oldval,mask2
1211 // or storeval,maskedoldval0,newval
1212 // sc success,storeval,0(alignedaddr)
1213 // beq success,$0,loopMBB
1214
1215 // atomic.swap
1216 // loopMBB:
1217 // ll oldval,0(alignedaddr)
1218 // and newval,incr2,mask
1219 // and maskedoldval0,oldval,mask2
1220 // or storeval,maskedoldval0,newval
1221 // sc success,storeval,0(alignedaddr)
1222 // beq success,$0,loopMBB
1223
1224 BB = loopMBB;
1225 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1226 if (Nand) {
1227 // and andres, oldval, incr2
1228 // nor binopres, $0, andres
1229 // and newval, binopres, mask
1230 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1231 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1232 .addReg(Mips::ZERO).addReg(AndRes);
1233 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1234 } else if (BinOpcode) {
1235 // <binop> binopres, oldval, incr2
1236 // and newval, binopres, mask
1237 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1238 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1239 } else {// atomic.swap
1240 // and newval, incr2, mask
1241 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1242 }
1243
1244 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1245 .addReg(OldVal).addReg(Mask2);
1246 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1247 .addReg(MaskedOldVal0).addReg(NewVal);
1248 BuildMI(BB, dl, TII->get(SC), Success)
1249 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1250 BuildMI(BB, dl, TII->get(Mips::BEQ))
1251 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1252
1253 // sinkMBB:
1254 // and maskedoldval1,oldval,mask
1255 // srl srlres,maskedoldval1,shiftamt
1256 // sll sllres,srlres,24
1257 // sra dest,sllres,24
1258 BB = sinkMBB;
1259 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1260
1261 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1262 .addReg(OldVal).addReg(Mask);
1263 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1264 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1265 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1266 .addReg(SrlRes).addImm(ShiftImm);
1267 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1268 .addReg(SllRes).addImm(ShiftImm);
1269
1270 MI->eraseFromParent(); // The instruction is gone now.
1271
1272 return exitMBB;
1273 }
1274
1275 MachineBasicBlock *
EmitAtomicCmpSwap(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size) const1276 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1277 MachineBasicBlock *BB,
1278 unsigned Size) const {
1279 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1280
1281 MachineFunction *MF = BB->getParent();
1282 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1283 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1284 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1285 DebugLoc dl = MI->getDebugLoc();
1286 unsigned LL, SC, ZERO, BNE, BEQ;
1287
1288 if (Size == 4) {
1289 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1290 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1291 ZERO = Mips::ZERO;
1292 BNE = Mips::BNE;
1293 BEQ = Mips::BEQ;
1294 }
1295 else {
1296 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1297 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1298 ZERO = Mips::ZERO_64;
1299 BNE = Mips::BNE64;
1300 BEQ = Mips::BEQ64;
1301 }
1302
1303 unsigned Dest = MI->getOperand(0).getReg();
1304 unsigned Ptr = MI->getOperand(1).getReg();
1305 unsigned OldVal = MI->getOperand(2).getReg();
1306 unsigned NewVal = MI->getOperand(3).getReg();
1307
1308 unsigned Success = RegInfo.createVirtualRegister(RC);
1309
1310 // insert new blocks after the current block
1311 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1312 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1313 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1314 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1315 MachineFunction::iterator It = BB;
1316 ++It;
1317 MF->insert(It, loop1MBB);
1318 MF->insert(It, loop2MBB);
1319 MF->insert(It, exitMBB);
1320
1321 // Transfer the remainder of BB and its successor edges to exitMBB.
1322 exitMBB->splice(exitMBB->begin(), BB,
1323 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1324 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1325
1326 // thisMBB:
1327 // ...
1328 // fallthrough --> loop1MBB
1329 BB->addSuccessor(loop1MBB);
1330 loop1MBB->addSuccessor(exitMBB);
1331 loop1MBB->addSuccessor(loop2MBB);
1332 loop2MBB->addSuccessor(loop1MBB);
1333 loop2MBB->addSuccessor(exitMBB);
1334
1335 // loop1MBB:
1336 // ll dest, 0(ptr)
1337 // bne dest, oldval, exitMBB
1338 BB = loop1MBB;
1339 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1340 BuildMI(BB, dl, TII->get(BNE))
1341 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1342
1343 // loop2MBB:
1344 // sc success, newval, 0(ptr)
1345 // beq success, $0, loop1MBB
1346 BB = loop2MBB;
1347 BuildMI(BB, dl, TII->get(SC), Success)
1348 .addReg(NewVal).addReg(Ptr).addImm(0);
1349 BuildMI(BB, dl, TII->get(BEQ))
1350 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1351
1352 MI->eraseFromParent(); // The instruction is gone now.
1353
1354 return exitMBB;
1355 }
1356
1357 MachineBasicBlock *
EmitAtomicCmpSwapPartword(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size) const1358 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1359 MachineBasicBlock *BB,
1360 unsigned Size) const {
1361 assert((Size == 1 || Size == 2) &&
1362 "Unsupported size for EmitAtomicCmpSwapPartial.");
1363
1364 MachineFunction *MF = BB->getParent();
1365 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1366 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1368 DebugLoc dl = MI->getDebugLoc();
1369 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1370 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1371
1372 unsigned Dest = MI->getOperand(0).getReg();
1373 unsigned Ptr = MI->getOperand(1).getReg();
1374 unsigned CmpVal = MI->getOperand(2).getReg();
1375 unsigned NewVal = MI->getOperand(3).getReg();
1376
1377 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1378 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1379 unsigned Mask = RegInfo.createVirtualRegister(RC);
1380 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1381 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1382 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1383 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1384 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1385 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1386 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1387 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1388 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1389 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1390 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1391 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1392 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1393 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1394 unsigned Success = RegInfo.createVirtualRegister(RC);
1395
1396 // insert new blocks after the current block
1397 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1398 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1399 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1400 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1401 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1402 MachineFunction::iterator It = BB;
1403 ++It;
1404 MF->insert(It, loop1MBB);
1405 MF->insert(It, loop2MBB);
1406 MF->insert(It, sinkMBB);
1407 MF->insert(It, exitMBB);
1408
1409 // Transfer the remainder of BB and its successor edges to exitMBB.
1410 exitMBB->splice(exitMBB->begin(), BB,
1411 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1412 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1413
1414 BB->addSuccessor(loop1MBB);
1415 loop1MBB->addSuccessor(sinkMBB);
1416 loop1MBB->addSuccessor(loop2MBB);
1417 loop2MBB->addSuccessor(loop1MBB);
1418 loop2MBB->addSuccessor(sinkMBB);
1419 sinkMBB->addSuccessor(exitMBB);
1420
1421 // FIXME: computation of newval2 can be moved to loop2MBB.
1422 // thisMBB:
1423 // addiu masklsb2,$0,-4 # 0xfffffffc
1424 // and alignedaddr,ptr,masklsb2
1425 // andi ptrlsb2,ptr,3
1426 // sll shiftamt,ptrlsb2,3
1427 // ori maskupper,$0,255 # 0xff
1428 // sll mask,maskupper,shiftamt
1429 // nor mask2,$0,mask
1430 // andi maskedcmpval,cmpval,255
1431 // sll shiftedcmpval,maskedcmpval,shiftamt
1432 // andi maskednewval,newval,255
1433 // sll shiftednewval,maskednewval,shiftamt
1434 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1435 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1436 .addReg(Mips::ZERO).addImm(-4);
1437 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1438 .addReg(Ptr).addReg(MaskLSB2);
1439 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1440 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1441 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1442 .addReg(Mips::ZERO).addImm(MaskImm);
1443 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1444 .addReg(ShiftAmt).addReg(MaskUpper);
1445 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1446 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1447 .addReg(CmpVal).addImm(MaskImm);
1448 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1449 .addReg(ShiftAmt).addReg(MaskedCmpVal);
1450 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1451 .addReg(NewVal).addImm(MaskImm);
1452 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1453 .addReg(ShiftAmt).addReg(MaskedNewVal);
1454
1455 // loop1MBB:
1456 // ll oldval,0(alginedaddr)
1457 // and maskedoldval0,oldval,mask
1458 // bne maskedoldval0,shiftedcmpval,sinkMBB
1459 BB = loop1MBB;
1460 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1461 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1462 .addReg(OldVal).addReg(Mask);
1463 BuildMI(BB, dl, TII->get(Mips::BNE))
1464 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1465
1466 // loop2MBB:
1467 // and maskedoldval1,oldval,mask2
1468 // or storeval,maskedoldval1,shiftednewval
1469 // sc success,storeval,0(alignedaddr)
1470 // beq success,$0,loop1MBB
1471 BB = loop2MBB;
1472 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1473 .addReg(OldVal).addReg(Mask2);
1474 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1475 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1476 BuildMI(BB, dl, TII->get(SC), Success)
1477 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1478 BuildMI(BB, dl, TII->get(Mips::BEQ))
1479 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1480
1481 // sinkMBB:
1482 // srl srlres,maskedoldval0,shiftamt
1483 // sll sllres,srlres,24
1484 // sra dest,sllres,24
1485 BB = sinkMBB;
1486 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1487
1488 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1489 .addReg(ShiftAmt).addReg(MaskedOldVal0);
1490 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1491 .addReg(SrlRes).addImm(ShiftImm);
1492 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1493 .addReg(SllRes).addImm(ShiftImm);
1494
1495 MI->eraseFromParent(); // The instruction is gone now.
1496
1497 return exitMBB;
1498 }
1499
1500 //===----------------------------------------------------------------------===//
1501 // Misc Lower Operation implementation
1502 //===----------------------------------------------------------------------===//
1503 SDValue MipsTargetLowering::
LowerBRCOND(SDValue Op,SelectionDAG & DAG) const1504 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1505 {
1506 // The first operand is the chain, the second is the condition, the third is
1507 // the block to branch to if the condition is true.
1508 SDValue Chain = Op.getOperand(0);
1509 SDValue Dest = Op.getOperand(2);
1510 DebugLoc dl = Op.getDebugLoc();
1511
1512 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1513
1514 // Return if flag is not set by a floating point comparison.
1515 if (CondRes.getOpcode() != MipsISD::FPCmp)
1516 return Op;
1517
1518 SDValue CCNode = CondRes.getOperand(2);
1519 Mips::CondCode CC =
1520 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1521 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1522
1523 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1524 Dest, CondRes);
1525 }
1526
1527 SDValue MipsTargetLowering::
LowerSELECT(SDValue Op,SelectionDAG & DAG) const1528 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1529 {
1530 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1531
1532 // Return if flag is not set by a floating point comparison.
1533 if (Cond.getOpcode() != MipsISD::FPCmp)
1534 return Op;
1535
1536 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1537 Op.getDebugLoc());
1538 }
1539
1540 SDValue MipsTargetLowering::
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const1541 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1542 {
1543 DebugLoc DL = Op.getDebugLoc();
1544 EVT Ty = Op.getOperand(0).getValueType();
1545 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1546 Op.getOperand(0), Op.getOperand(1),
1547 Op.getOperand(4));
1548
1549 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1550 Op.getOperand(3));
1551 }
1552
LowerSETCC(SDValue Op,SelectionDAG & DAG) const1553 SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1554 SDValue Cond = CreateFPCmp(DAG, Op);
1555
1556 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1557 "Floating point operand expected.");
1558
1559 SDValue True = DAG.getConstant(1, MVT::i32);
1560 SDValue False = DAG.getConstant(0, MVT::i32);
1561
1562 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1563 }
1564
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1565 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1566 SelectionDAG &DAG) const {
1567 // FIXME there isn't actually debug info here
1568 DebugLoc dl = Op.getDebugLoc();
1569 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1570
1571 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1572 SDVTList VTs = DAG.getVTList(MVT::i32);
1573
1574 const MipsTargetObjectFile &TLOF = (const MipsTargetObjectFile&)getObjFileLowering();
1575
1576 // %gp_rel relocation
1577 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1578 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1579 MipsII::MO_GPREL);
1580 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1581 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1582 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
1583 }
1584 // %hi/%lo relocation
1585 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1586 MipsII::MO_ABS_HI);
1587 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1588 MipsII::MO_ABS_LO);
1589 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1590 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1591 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1592 }
1593
1594 EVT ValTy = Op.getValueType();
1595 bool HasGotOfst = (GV->hasInternalLinkage() ||
1596 (GV->hasLocalLinkage() && !isa<Function>(GV)));
1597 unsigned GotFlag = HasMips64 ?
1598 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
1599 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
1600 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
1601 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
1602 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1603 MachinePointerInfo(), false, false, false, 0);
1604 // On functions and global targets not internal linked only
1605 // a load from got/GP is necessary for PIC to work.
1606 if (!HasGotOfst)
1607 return ResNode;
1608 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
1609 HasMips64 ? MipsII::MO_GOT_OFST :
1610 MipsII::MO_ABS_LO);
1611 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1612 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
1613 }
1614
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1615 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1616 SelectionDAG &DAG) const {
1617 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1618 // FIXME there isn't actually debug info here
1619 DebugLoc dl = Op.getDebugLoc();
1620
1621 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1622 // %hi/%lo relocation
1623 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
1624 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
1625 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1626 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1627 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1628 }
1629
1630 EVT ValTy = Op.getValueType();
1631 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1632 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1633 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
1634 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1635 GetGlobalReg(DAG, ValTy), BAGOTOffset);
1636 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
1637 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
1638 MachinePointerInfo(), false, false, false, 0);
1639 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1640 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1641 }
1642
1643 SDValue MipsTargetLowering::
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1644 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1645 {
1646 // If the relocation model is PIC, use the General Dynamic TLS Model or
1647 // Local Dynamic TLS model, otherwise use the Initial Exec or
1648 // Local Exec TLS Model.
1649
1650 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1651 DebugLoc dl = GA->getDebugLoc();
1652 const GlobalValue *GV = GA->getGlobal();
1653 EVT PtrVT = getPointerTy();
1654
1655 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1656
1657 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1658 // General Dynamic and Local Dynamic TLS Model.
1659 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1660 : MipsII::MO_TLSGD;
1661
1662 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
1663 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1664 GetGlobalReg(DAG, PtrVT), TGA);
1665 unsigned PtrSize = PtrVT.getSizeInBits();
1666 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1667
1668 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1669
1670 ArgListTy Args;
1671 ArgListEntry Entry;
1672 Entry.Node = Argument;
1673 Entry.Ty = PtrTy;
1674 Args.push_back(Entry);
1675
1676 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1677 false, false, false, false, 0, CallingConv::C,
1678 /*isTailCall=*/false, /*doesNotRet=*/false,
1679 /*isReturnValueUsed=*/true,
1680 TlsGetAddr, Args, DAG, dl);
1681 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1682
1683 SDValue Ret = CallResult.first;
1684
1685 if (model != TLSModel::LocalDynamic)
1686 return Ret;
1687
1688 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1689 MipsII::MO_DTPREL_HI);
1690 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1691 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1692 MipsII::MO_DTPREL_LO);
1693 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1694 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1695 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
1696 }
1697
1698 SDValue Offset;
1699 if (model == TLSModel::InitialExec) {
1700 // Initial Exec TLS Model
1701 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1702 MipsII::MO_GOTTPREL);
1703 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1704 TGA);
1705 Offset = DAG.getLoad(PtrVT, dl,
1706 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1707 false, false, false, 0);
1708 } else {
1709 // Local Exec TLS Model
1710 assert(model == TLSModel::LocalExec);
1711 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1712 MipsII::MO_TPREL_HI);
1713 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1714 MipsII::MO_TPREL_LO);
1715 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1716 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1717 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1718 }
1719
1720 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1721 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1722 }
1723
1724 SDValue MipsTargetLowering::
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const1725 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1726 {
1727 SDValue HiPart, JTI, JTILo;
1728 // FIXME there isn't actually debug info here
1729 DebugLoc dl = Op.getDebugLoc();
1730 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1731 EVT PtrVT = Op.getValueType();
1732 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1733
1734 if (!IsPIC && !IsN64) {
1735 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1736 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1737 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
1738 } else {// Emit Load from Global Pointer
1739 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1740 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1741 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
1742 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1743 JTI);
1744 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1745 MachinePointerInfo(), false, false, false, 0);
1746 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
1747 }
1748
1749 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1750 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
1751 }
1752
1753 SDValue MipsTargetLowering::
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const1754 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1755 {
1756 SDValue ResNode;
1757 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1758 const Constant *C = N->getConstVal();
1759 // FIXME there isn't actually debug info here
1760 DebugLoc dl = Op.getDebugLoc();
1761
1762 // gp_rel relocation
1763 // FIXME: we should reference the constant pool using small data sections,
1764 // but the asm printer currently doesn't support this feature without
1765 // hacking it. This feature should come soon so we can uncomment the
1766 // stuff below.
1767 //if (IsInSmallSection(C->getType())) {
1768 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1769 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1770 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1771
1772 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1773 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1774 N->getOffset(), MipsII::MO_ABS_HI);
1775 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1776 N->getOffset(), MipsII::MO_ABS_LO);
1777 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1778 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1779 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1780 } else {
1781 EVT ValTy = Op.getValueType();
1782 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1783 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1784 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1785 N->getOffset(), GOTFlag);
1786 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
1787 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1788 MachinePointerInfo::getConstantPool(), false,
1789 false, false, 0);
1790 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1791 N->getOffset(), OFSTFlag);
1792 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1793 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1794 }
1795
1796 return ResNode;
1797 }
1798
LowerVASTART(SDValue Op,SelectionDAG & DAG) const1799 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1800 MachineFunction &MF = DAG.getMachineFunction();
1801 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1802
1803 DebugLoc dl = Op.getDebugLoc();
1804 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1805 getPointerTy());
1806
1807 // vastart just stores the address of the VarArgsFrameIndex slot into the
1808 // memory location argument.
1809 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1810 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1811 MachinePointerInfo(SV), false, false, 0);
1812 }
1813
LowerFCOPYSIGN32(SDValue Op,SelectionDAG & DAG,bool HasR2)1814 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1815 EVT TyX = Op.getOperand(0).getValueType();
1816 EVT TyY = Op.getOperand(1).getValueType();
1817 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1818 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1819 DebugLoc DL = Op.getDebugLoc();
1820 SDValue Res;
1821
1822 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1823 // to i32.
1824 SDValue X = (TyX == MVT::f32) ?
1825 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1826 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1827 Const1);
1828 SDValue Y = (TyY == MVT::f32) ?
1829 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1830 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1831 Const1);
1832
1833 if (HasR2) {
1834 // ext E, Y, 31, 1 ; extract bit31 of Y
1835 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1836 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1837 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1838 } else {
1839 // sll SllX, X, 1
1840 // srl SrlX, SllX, 1
1841 // srl SrlY, Y, 31
1842 // sll SllY, SrlX, 31
1843 // or Or, SrlX, SllY
1844 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1845 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1846 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1847 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1848 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1849 }
1850
1851 if (TyX == MVT::f32)
1852 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1853
1854 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1855 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1856 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1857 }
1858
LowerFCOPYSIGN64(SDValue Op,SelectionDAG & DAG,bool HasR2)1859 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1860 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1861 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1862 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1863 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1864 DebugLoc DL = Op.getDebugLoc();
1865
1866 // Bitcast to integer nodes.
1867 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1868 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1869
1870 if (HasR2) {
1871 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1872 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1873 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1874 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1875
1876 if (WidthX > WidthY)
1877 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1878 else if (WidthY > WidthX)
1879 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1880
1881 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1882 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1883 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1884 }
1885
1886 // (d)sll SllX, X, 1
1887 // (d)srl SrlX, SllX, 1
1888 // (d)srl SrlY, Y, width(Y)-1
1889 // (d)sll SllY, SrlX, width(Y)-1
1890 // or Or, SrlX, SllY
1891 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1892 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1893 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1894 DAG.getConstant(WidthY - 1, MVT::i32));
1895
1896 if (WidthX > WidthY)
1897 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1898 else if (WidthY > WidthX)
1899 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1900
1901 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1902 DAG.getConstant(WidthX - 1, MVT::i32));
1903 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1904 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1905 }
1906
1907 SDValue
LowerFCOPYSIGN(SDValue Op,SelectionDAG & DAG) const1908 MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1909 if (Subtarget->hasMips64())
1910 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
1911
1912 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
1913 }
1914
LowerFABS32(SDValue Op,SelectionDAG & DAG,bool HasR2)1915 static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1916 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1917 DebugLoc DL = Op.getDebugLoc();
1918
1919 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1920 // to i32.
1921 SDValue X = (Op.getValueType() == MVT::f32) ?
1922 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1923 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1924 Const1);
1925
1926 // Clear MSB.
1927 if (HasR2)
1928 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1929 DAG.getRegister(Mips::ZERO, MVT::i32),
1930 DAG.getConstant(31, MVT::i32), Const1, X);
1931 else {
1932 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1933 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1934 }
1935
1936 if (Op.getValueType() == MVT::f32)
1937 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1938
1939 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1940 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1941 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1942 }
1943
LowerFABS64(SDValue Op,SelectionDAG & DAG,bool HasR2)1944 static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1945 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1946 DebugLoc DL = Op.getDebugLoc();
1947
1948 // Bitcast to integer node.
1949 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1950
1951 // Clear MSB.
1952 if (HasR2)
1953 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1954 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1955 DAG.getConstant(63, MVT::i32), Const1, X);
1956 else {
1957 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1958 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1959 }
1960
1961 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1962 }
1963
1964 SDValue
LowerFABS(SDValue Op,SelectionDAG & DAG) const1965 MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
1966 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1967 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1968
1969 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1970 }
1971
1972 SDValue MipsTargetLowering::
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const1973 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1974 // check the depth
1975 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1976 "Frame address can only be determined for current frame.");
1977
1978 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1979 MFI->setFrameAddressIsTaken(true);
1980 EVT VT = Op.getValueType();
1981 DebugLoc dl = Op.getDebugLoc();
1982 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1983 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1984 return FrameAddr;
1985 }
1986
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const1987 SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
1988 SelectionDAG &DAG) const {
1989 // check the depth
1990 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1991 "Return address can be determined only for current frame.");
1992
1993 MachineFunction &MF = DAG.getMachineFunction();
1994 MachineFrameInfo *MFI = MF.getFrameInfo();
1995 EVT VT = Op.getValueType();
1996 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1997 MFI->setReturnAddressIsTaken(true);
1998
1999 // Return RA, which contains the return address. Mark it an implicit live-in.
2000 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2001 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2002 }
2003
2004 // TODO: set SType according to the desired memory barrier behavior.
2005 SDValue
LowerMEMBARRIER(SDValue Op,SelectionDAG & DAG) const2006 MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2007 unsigned SType = 0;
2008 DebugLoc dl = Op.getDebugLoc();
2009 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2010 DAG.getConstant(SType, MVT::i32));
2011 }
2012
LowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const2013 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2014 SelectionDAG &DAG) const {
2015 // FIXME: Need pseudo-fence for 'singlethread' fences
2016 // FIXME: Set SType for weaker fences where supported/appropriate.
2017 unsigned SType = 0;
2018 DebugLoc dl = Op.getDebugLoc();
2019 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2020 DAG.getConstant(SType, MVT::i32));
2021 }
2022
LowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const2023 SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2024 SelectionDAG &DAG) const {
2025 DebugLoc DL = Op.getDebugLoc();
2026 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2027 SDValue Shamt = Op.getOperand(2);
2028
2029 // if shamt < 32:
2030 // lo = (shl lo, shamt)
2031 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2032 // else:
2033 // lo = 0
2034 // hi = (shl lo, shamt[4:0])
2035 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2036 DAG.getConstant(-1, MVT::i32));
2037 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2038 DAG.getConstant(1, MVT::i32));
2039 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2040 Not);
2041 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2042 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2043 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2044 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2045 DAG.getConstant(0x20, MVT::i32));
2046 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2047 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2048 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2049
2050 SDValue Ops[2] = {Lo, Hi};
2051 return DAG.getMergeValues(Ops, 2, DL);
2052 }
2053
LowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const2054 SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2055 bool IsSRA) const {
2056 DebugLoc DL = Op.getDebugLoc();
2057 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2058 SDValue Shamt = Op.getOperand(2);
2059
2060 // if shamt < 32:
2061 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2062 // if isSRA:
2063 // hi = (sra hi, shamt)
2064 // else:
2065 // hi = (srl hi, shamt)
2066 // else:
2067 // if isSRA:
2068 // lo = (sra hi, shamt[4:0])
2069 // hi = (sra hi, 31)
2070 // else:
2071 // lo = (srl hi, shamt[4:0])
2072 // hi = 0
2073 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2074 DAG.getConstant(-1, MVT::i32));
2075 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2076 DAG.getConstant(1, MVT::i32));
2077 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2078 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2079 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2080 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2081 Hi, Shamt);
2082 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2083 DAG.getConstant(0x20, MVT::i32));
2084 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2085 DAG.getConstant(31, MVT::i32));
2086 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2087 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2088 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2089 ShiftRightHi);
2090
2091 SDValue Ops[2] = {Lo, Hi};
2092 return DAG.getMergeValues(Ops, 2, DL);
2093 }
2094
CreateLoadLR(unsigned Opc,SelectionDAG & DAG,LoadSDNode * LD,SDValue Chain,SDValue Src,unsigned Offset)2095 static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2096 SDValue Chain, SDValue Src, unsigned Offset) {
2097 SDValue Ptr = LD->getBasePtr();
2098 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2099 EVT BasePtrVT = Ptr.getValueType();
2100 DebugLoc DL = LD->getDebugLoc();
2101 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2102
2103 if (Offset)
2104 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2105 DAG.getConstant(Offset, BasePtrVT));
2106
2107 SDValue Ops[] = { Chain, Ptr, Src };
2108 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2109 LD->getMemOperand());
2110 }
2111
2112 // Expand an unaligned 32 or 64-bit integer load node.
LowerLOAD(SDValue Op,SelectionDAG & DAG) const2113 SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2114 LoadSDNode *LD = cast<LoadSDNode>(Op);
2115 EVT MemVT = LD->getMemoryVT();
2116
2117 // Return if load is aligned or if MemVT is neither i32 nor i64.
2118 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2119 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2120 return SDValue();
2121
2122 bool IsLittle = Subtarget->isLittle();
2123 EVT VT = Op.getValueType();
2124 ISD::LoadExtType ExtType = LD->getExtensionType();
2125 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2126
2127 assert((VT == MVT::i32) || (VT == MVT::i64));
2128
2129 // Expand
2130 // (set dst, (i64 (load baseptr)))
2131 // to
2132 // (set tmp, (ldl (add baseptr, 7), undef))
2133 // (set dst, (ldr baseptr, tmp))
2134 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2135 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2136 IsLittle ? 7 : 0);
2137 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2138 IsLittle ? 0 : 7);
2139 }
2140
2141 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2142 IsLittle ? 3 : 0);
2143 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2144 IsLittle ? 0 : 3);
2145
2146 // Expand
2147 // (set dst, (i32 (load baseptr))) or
2148 // (set dst, (i64 (sextload baseptr))) or
2149 // (set dst, (i64 (extload baseptr)))
2150 // to
2151 // (set tmp, (lwl (add baseptr, 3), undef))
2152 // (set dst, (lwr baseptr, tmp))
2153 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2154 (ExtType == ISD::EXTLOAD))
2155 return LWR;
2156
2157 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2158
2159 // Expand
2160 // (set dst, (i64 (zextload baseptr)))
2161 // to
2162 // (set tmp0, (lwl (add baseptr, 3), undef))
2163 // (set tmp1, (lwr baseptr, tmp0))
2164 // (set tmp2, (shl tmp1, 32))
2165 // (set dst, (srl tmp2, 32))
2166 DebugLoc DL = LD->getDebugLoc();
2167 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2168 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2169 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2170 SDValue Ops[] = { SRL, LWR.getValue(1) };
2171 return DAG.getMergeValues(Ops, 2, DL);
2172 }
2173
CreateStoreLR(unsigned Opc,SelectionDAG & DAG,StoreSDNode * SD,SDValue Chain,unsigned Offset)2174 static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2175 SDValue Chain, unsigned Offset) {
2176 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2177 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2178 DebugLoc DL = SD->getDebugLoc();
2179 SDVTList VTList = DAG.getVTList(MVT::Other);
2180
2181 if (Offset)
2182 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2183 DAG.getConstant(Offset, BasePtrVT));
2184
2185 SDValue Ops[] = { Chain, Value, Ptr };
2186 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2187 SD->getMemOperand());
2188 }
2189
2190 // Expand an unaligned 32 or 64-bit integer store node.
LowerSTORE(SDValue Op,SelectionDAG & DAG) const2191 SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2192 StoreSDNode *SD = cast<StoreSDNode>(Op);
2193 EVT MemVT = SD->getMemoryVT();
2194
2195 // Return if store is aligned or if MemVT is neither i32 nor i64.
2196 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2197 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2198 return SDValue();
2199
2200 bool IsLittle = Subtarget->isLittle();
2201 SDValue Value = SD->getValue(), Chain = SD->getChain();
2202 EVT VT = Value.getValueType();
2203
2204 // Expand
2205 // (store val, baseptr) or
2206 // (truncstore val, baseptr)
2207 // to
2208 // (swl val, (add baseptr, 3))
2209 // (swr val, baseptr)
2210 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2211 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2212 IsLittle ? 3 : 0);
2213 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2214 }
2215
2216 assert(VT == MVT::i64);
2217
2218 // Expand
2219 // (store val, baseptr)
2220 // to
2221 // (sdl val, (add baseptr, 7))
2222 // (sdr val, baseptr)
2223 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2224 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2225 }
2226
2227 //===----------------------------------------------------------------------===//
2228 // Calling Convention Implementation
2229 //===----------------------------------------------------------------------===//
2230
2231 //===----------------------------------------------------------------------===//
2232 // TODO: Implement a generic logic using tblgen that can support this.
2233 // Mips O32 ABI rules:
2234 // ---
2235 // i32 - Passed in A0, A1, A2, A3 and stack
2236 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2237 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2238 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2239 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2240 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2241 // go to stack.
2242 //
2243 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2244 //===----------------------------------------------------------------------===//
2245
CC_MipsO32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2246 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2247 MVT LocVT, CCValAssign::LocInfo LocInfo,
2248 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2249
2250 static const unsigned IntRegsSize=4, FloatRegsSize=2;
2251
2252 static const uint16_t IntRegs[] = {
2253 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2254 };
2255 static const uint16_t F32Regs[] = {
2256 Mips::F12, Mips::F14
2257 };
2258 static const uint16_t F64Regs[] = {
2259 Mips::D6, Mips::D7
2260 };
2261
2262 // ByVal Args
2263 if (ArgFlags.isByVal()) {
2264 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2265 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2266 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2267 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2268 r < std::min(IntRegsSize, NextReg); ++r)
2269 State.AllocateReg(IntRegs[r]);
2270 return false;
2271 }
2272
2273 // Promote i8 and i16
2274 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2275 LocVT = MVT::i32;
2276 if (ArgFlags.isSExt())
2277 LocInfo = CCValAssign::SExt;
2278 else if (ArgFlags.isZExt())
2279 LocInfo = CCValAssign::ZExt;
2280 else
2281 LocInfo = CCValAssign::AExt;
2282 }
2283
2284 unsigned Reg;
2285
2286 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2287 // is true: function is vararg, argument is 3rd or higher, there is previous
2288 // argument which is not f32 or f64.
2289 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2290 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2291 unsigned OrigAlign = ArgFlags.getOrigAlign();
2292 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2293
2294 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2295 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2296 // If this is the first part of an i64 arg,
2297 // the allocated register must be either A0 or A2.
2298 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2299 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2300 LocVT = MVT::i32;
2301 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2302 // Allocate int register and shadow next int register. If first
2303 // available register is Mips::A1 or Mips::A3, shadow it too.
2304 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2305 if (Reg == Mips::A1 || Reg == Mips::A3)
2306 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2307 State.AllocateReg(IntRegs, IntRegsSize);
2308 LocVT = MVT::i32;
2309 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2310 // we are guaranteed to find an available float register
2311 if (ValVT == MVT::f32) {
2312 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2313 // Shadow int register
2314 State.AllocateReg(IntRegs, IntRegsSize);
2315 } else {
2316 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2317 // Shadow int registers
2318 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2319 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2320 State.AllocateReg(IntRegs, IntRegsSize);
2321 State.AllocateReg(IntRegs, IntRegsSize);
2322 }
2323 } else
2324 llvm_unreachable("Cannot handle this ValVT.");
2325
2326 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2327 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2328
2329 if (!Reg)
2330 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2331 else
2332 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2333
2334 return false; // CC must always match
2335 }
2336
2337 static const uint16_t Mips64IntRegs[8] =
2338 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2339 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
2340 static const uint16_t Mips64DPRegs[8] =
2341 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2342 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2343
CC_Mips64Byval(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2344 static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2345 CCValAssign::LocInfo LocInfo,
2346 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2347 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2348 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2349 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2350
2351 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2352
2353 // If byval is 16-byte aligned, the first arg register must be even.
2354 if ((Align == 16) && (FirstIdx % 2)) {
2355 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2356 ++FirstIdx;
2357 }
2358
2359 // Mark the registers allocated.
2360 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2361 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2362
2363 // Allocate space on caller's stack.
2364 unsigned Offset = State.AllocateStack(Size, Align);
2365
2366 if (FirstIdx < 8)
2367 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
2368 LocVT, LocInfo));
2369 else
2370 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2371
2372 return true;
2373 }
2374
2375 #include "MipsGenCallingConv.inc"
2376
2377 static void
AnalyzeMips64CallOperands(CCState & CCInfo,const SmallVectorImpl<ISD::OutputArg> & Outs)2378 AnalyzeMips64CallOperands(CCState &CCInfo,
2379 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2380 unsigned NumOps = Outs.size();
2381 for (unsigned i = 0; i != NumOps; ++i) {
2382 MVT ArgVT = Outs[i].VT;
2383 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2384 bool R;
2385
2386 if (Outs[i].IsFixed)
2387 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2388 else
2389 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2390
2391 if (R) {
2392 #ifndef NDEBUG
2393 dbgs() << "Call operand #" << i << " has unhandled type "
2394 << EVT(ArgVT).getEVTString();
2395 #endif
2396 llvm_unreachable(0);
2397 }
2398 }
2399 }
2400
2401 //===----------------------------------------------------------------------===//
2402 // Call Calling Convention Implementation
2403 //===----------------------------------------------------------------------===//
2404
2405 static const unsigned O32IntRegsSize = 4;
2406
2407 static const uint16_t O32IntRegs[] = {
2408 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2409 };
2410
2411 // Return next O32 integer argument register.
getNextIntArgReg(unsigned Reg)2412 static unsigned getNextIntArgReg(unsigned Reg) {
2413 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2414 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2415 }
2416
2417 // Write ByVal Arg to arg registers and stack.
2418 static void
WriteByValArg(SDValue Chain,DebugLoc dl,SmallVector<std::pair<unsigned,SDValue>,16> & RegsToPass,SmallVector<SDValue,8> & MemOpChains,SDValue StackPtr,MachineFrameInfo * MFI,SelectionDAG & DAG,SDValue Arg,const CCValAssign & VA,const ISD::ArgFlagsTy & Flags,MVT PtrType,bool isLittle)2419 WriteByValArg(SDValue Chain, DebugLoc dl,
2420 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
2421 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
2422 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2423 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
2424 MVT PtrType, bool isLittle) {
2425 unsigned LocMemOffset = VA.getLocMemOffset();
2426 unsigned Offset = 0;
2427 uint32_t RemainingSize = Flags.getByValSize();
2428 unsigned ByValAlign = Flags.getByValAlign();
2429
2430 // Copy the first 4 words of byval arg to registers A0 - A3.
2431 // FIXME: Use a stricter alignment if it enables better optimization in passes
2432 // run later.
2433 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2434 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
2435 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2436 DAG.getConstant(Offset, MVT::i32));
2437 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
2438 MachinePointerInfo(), false, false, false,
2439 std::min(ByValAlign, (unsigned )4));
2440 MemOpChains.push_back(LoadVal.getValue(1));
2441 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2442 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2443 }
2444
2445 if (RemainingSize == 0)
2446 return;
2447
2448 // If there still is a register available for argument passing, write the
2449 // remaining part of the structure to it using subword loads and shifts.
2450 if (LocMemOffset < 4 * 4) {
2451 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2452 "There must be one to three bytes remaining.");
2453 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2454 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2455 DAG.getConstant(Offset, MVT::i32));
2456 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2457 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2458 LoadPtr, MachinePointerInfo(),
2459 MVT::getIntegerVT(LoadSize * 8), false,
2460 false, Alignment);
2461 MemOpChains.push_back(LoadVal.getValue(1));
2462
2463 // If target is big endian, shift it to the most significant half-word or
2464 // byte.
2465 if (!isLittle)
2466 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2467 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2468
2469 Offset += LoadSize;
2470 RemainingSize -= LoadSize;
2471
2472 // Read second subword if necessary.
2473 if (RemainingSize != 0) {
2474 assert(RemainingSize == 1 && "There must be one byte remaining.");
2475 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2476 DAG.getConstant(Offset, MVT::i32));
2477 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2478 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2479 LoadPtr, MachinePointerInfo(),
2480 MVT::i8, false, false, Alignment);
2481 MemOpChains.push_back(Subword.getValue(1));
2482 // Insert the loaded byte to LoadVal.
2483 // FIXME: Use INS if supported by target.
2484 unsigned ShiftAmt = isLittle ? 16 : 8;
2485 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2486 DAG.getConstant(ShiftAmt, MVT::i32));
2487 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2488 }
2489
2490 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2491 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2492 return;
2493 }
2494
2495 // Copy remaining part of byval arg using memcpy.
2496 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2497 DAG.getConstant(Offset, MVT::i32));
2498 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr,
2499 DAG.getIntPtrConstant(LocMemOffset));
2500 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2501 DAG.getConstant(RemainingSize, MVT::i32),
2502 std::min(ByValAlign, (unsigned)4),
2503 /*isVolatile=*/false, /*AlwaysInline=*/false,
2504 MachinePointerInfo(0), MachinePointerInfo(0));
2505 MemOpChains.push_back(Chain);
2506 }
2507
2508 // Copy Mips64 byVal arg to registers and stack.
2509 void static
PassByValArg64(SDValue Chain,DebugLoc dl,SmallVector<std::pair<unsigned,SDValue>,16> & RegsToPass,SmallVector<SDValue,8> & MemOpChains,SDValue StackPtr,MachineFrameInfo * MFI,SelectionDAG & DAG,SDValue Arg,const CCValAssign & VA,const ISD::ArgFlagsTy & Flags,EVT PtrTy,bool isLittle)2510 PassByValArg64(SDValue Chain, DebugLoc dl,
2511 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
2512 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
2513 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2514 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
2515 EVT PtrTy, bool isLittle) {
2516 unsigned ByValSize = Flags.getByValSize();
2517 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2518 bool IsRegLoc = VA.isRegLoc();
2519 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2520 unsigned LocMemOffset = 0;
2521 unsigned MemCpySize = ByValSize;
2522
2523 if (!IsRegLoc)
2524 LocMemOffset = VA.getLocMemOffset();
2525 else {
2526 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
2527 VA.getLocReg());
2528 const uint16_t *RegEnd = Mips64IntRegs + 8;
2529
2530 // Copy double words to registers.
2531 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2532 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2533 DAG.getConstant(Offset, PtrTy));
2534 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2535 MachinePointerInfo(), false, false, false,
2536 Alignment);
2537 MemOpChains.push_back(LoadVal.getValue(1));
2538 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2539 }
2540
2541 // Return if the struct has been fully copied.
2542 if (!(MemCpySize = ByValSize - Offset))
2543 return;
2544
2545 // If there is an argument register available, copy the remainder of the
2546 // byval argument with sub-doubleword loads and shifts.
2547 if (Reg != RegEnd) {
2548 assert((ByValSize < Offset + 8) &&
2549 "Size of the remainder should be smaller than 8-byte.");
2550 SDValue Val;
2551 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2552 unsigned RemSize = ByValSize - Offset;
2553
2554 if (RemSize < LoadSize)
2555 continue;
2556
2557 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2558 DAG.getConstant(Offset, PtrTy));
2559 SDValue LoadVal =
2560 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2561 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2562 false, false, Alignment);
2563 MemOpChains.push_back(LoadVal.getValue(1));
2564
2565 // Offset in number of bits from double word boundary.
2566 unsigned OffsetDW = (Offset % 8) * 8;
2567 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2568 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2569 DAG.getConstant(Shamt, MVT::i32));
2570
2571 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2572 Shift;
2573 Offset += LoadSize;
2574 Alignment = std::min(Alignment, LoadSize);
2575 }
2576
2577 RegsToPass.push_back(std::make_pair(*Reg, Val));
2578 return;
2579 }
2580 }
2581
2582 assert(MemCpySize && "MemCpySize must not be zero.");
2583
2584 // Copy remainder of byval arg to it with memcpy.
2585 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2586 DAG.getConstant(Offset, PtrTy));
2587 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr,
2588 DAG.getIntPtrConstant(LocMemOffset));
2589 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2590 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2591 /*isVolatile=*/false, /*AlwaysInline=*/false,
2592 MachinePointerInfo(0), MachinePointerInfo(0));
2593 MemOpChains.push_back(Chain);
2594 }
2595
2596 /// LowerCall - functions arguments are copied from virtual regs to
2597 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2598 /// TODO: isTailCall.
2599 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const2600 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2601 SmallVectorImpl<SDValue> &InVals) const {
2602 SelectionDAG &DAG = CLI.DAG;
2603 DebugLoc &dl = CLI.DL;
2604 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2605 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2606 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2607 SDValue Chain = CLI.Chain;
2608 SDValue Callee = CLI.Callee;
2609 bool &isTailCall = CLI.IsTailCall;
2610 CallingConv::ID CallConv = CLI.CallConv;
2611 bool isVarArg = CLI.IsVarArg;
2612
2613 // MIPs target does not yet support tail call optimization.
2614 isTailCall = false;
2615
2616 MachineFunction &MF = DAG.getMachineFunction();
2617 MachineFrameInfo *MFI = MF.getFrameInfo();
2618 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2619 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2620 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2621
2622 // Analyze operands of the call, assigning locations to each operand.
2623 SmallVector<CCValAssign, 16> ArgLocs;
2624 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2625 getTargetMachine(), ArgLocs, *DAG.getContext());
2626
2627 if (CallConv == CallingConv::Fast)
2628 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC);
2629 else if (IsO32)
2630 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
2631 else if (HasMips64)
2632 AnalyzeMips64CallOperands(CCInfo, Outs);
2633 else
2634 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
2635
2636 // Get a count of how many bytes are to be pushed on the stack.
2637 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2638 unsigned StackAlignment = TFL->getStackAlignment();
2639 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2640
2641 // Update size of the maximum argument space.
2642 // For O32, a minimum of four words (16 bytes) of argument space is
2643 // allocated.
2644 if (IsO32 && (CallConv != CallingConv::Fast))
2645 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2646
2647 // Chain is the output chain of the last Load/Store or CopyToReg node.
2648 // ByValChain is the output chain of the last Memcpy node created for copying
2649 // byval arguments to the stack.
2650 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2651 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2652
2653 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2654 IsN64 ? Mips::SP_64 : Mips::SP,
2655 getPointerTy());
2656
2657 if (MipsFI->getMaxCallFrameSize() < NextStackOffset)
2658 MipsFI->setMaxCallFrameSize(NextStackOffset);
2659
2660 // With EABI is it possible to have 16 args on registers.
2661 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2662 SmallVector<SDValue, 8> MemOpChains;
2663
2664 // Walk the register/memloc assignments, inserting copies/loads.
2665 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2666 SDValue Arg = OutVals[i];
2667 CCValAssign &VA = ArgLocs[i];
2668 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2669 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2670
2671 // ByVal Arg.
2672 if (Flags.isByVal()) {
2673 assert(Flags.getByValSize() &&
2674 "ByVal args of size 0 should have been ignored by front-end.");
2675 if (IsO32)
2676 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr,
2677 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2678 Subtarget->isLittle());
2679 else
2680 PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr,
2681 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2682 Subtarget->isLittle());
2683 continue;
2684 }
2685
2686 // Promote the value if needed.
2687 switch (VA.getLocInfo()) {
2688 default: llvm_unreachable("Unknown loc info!");
2689 case CCValAssign::Full:
2690 if (VA.isRegLoc()) {
2691 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2692 (ValVT == MVT::f64 && LocVT == MVT::i64))
2693 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2694 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2695 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2696 Arg, DAG.getConstant(0, MVT::i32));
2697 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2698 Arg, DAG.getConstant(1, MVT::i32));
2699 if (!Subtarget->isLittle())
2700 std::swap(Lo, Hi);
2701 unsigned LocRegLo = VA.getLocReg();
2702 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2703 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2704 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2705 continue;
2706 }
2707 }
2708 break;
2709 case CCValAssign::SExt:
2710 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
2711 break;
2712 case CCValAssign::ZExt:
2713 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
2714 break;
2715 case CCValAssign::AExt:
2716 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
2717 break;
2718 }
2719
2720 // Arguments that can be passed on register must be kept at
2721 // RegsToPass vector
2722 if (VA.isRegLoc()) {
2723 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2724 continue;
2725 }
2726
2727 // Register can't get to this point...
2728 assert(VA.isMemLoc());
2729
2730 // emit ISD::STORE whichs stores the
2731 // parameter value to a stack Location
2732 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
2733 DAG.getIntPtrConstant(VA.getLocMemOffset()));
2734 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2735 MachinePointerInfo(), false, false, 0));
2736 }
2737
2738 // Transform all store nodes into one single node because all store
2739 // nodes are independent of each other.
2740 if (!MemOpChains.empty())
2741 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2742 &MemOpChains[0], MemOpChains.size());
2743
2744 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2745 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2746 // node so that legalize doesn't hack it.
2747 unsigned char OpFlag;
2748 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2749 bool GlobalOrExternal = false;
2750 SDValue CalleeLo;
2751
2752 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2753 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2754 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2755 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2756 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2757 OpFlag);
2758 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
2759 0, LoFlag);
2760 } else {
2761 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
2762 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2763 getPointerTy(), 0, OpFlag);
2764 }
2765
2766 GlobalOrExternal = true;
2767 }
2768 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2769 if (IsN64 || (!IsO32 && IsPIC))
2770 OpFlag = MipsII::MO_GOT_DISP;
2771 else if (!IsPIC) // !N64 && static
2772 OpFlag = MipsII::MO_NO_FLAG;
2773 else // O32 & PIC
2774 OpFlag = MipsII::MO_GOT_CALL;
2775 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2776 OpFlag);
2777 GlobalOrExternal = true;
2778 }
2779
2780 SDValue InFlag;
2781
2782 // Create nodes that load address of callee and copy it to T9
2783 if (IsPICCall) {
2784 if (GlobalOrExternal) {
2785 // Load callee address
2786 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2787 GetGlobalReg(DAG, getPointerTy()), Callee);
2788 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2789 Callee, MachinePointerInfo::getGOT(),
2790 false, false, false, 0);
2791
2792 // Use GOT+LO if callee has internal linkage.
2793 if (CalleeLo.getNode()) {
2794 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2795 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
2796 } else
2797 Callee = LoadValue;
2798 }
2799 }
2800
2801 // T9 register operand.
2802 SDValue T9;
2803
2804 // T9 should contain the address of the callee function if
2805 // -reloction-model=pic or it is an indirect call.
2806 if (IsPICCall || !GlobalOrExternal) {
2807 // copy to T9
2808 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2809 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
2810 InFlag = Chain.getValue(1);
2811
2812 if (Subtarget->inMips16Mode())
2813 T9 = DAG.getRegister(T9Reg, getPointerTy());
2814 else
2815 Callee = DAG.getRegister(T9Reg, getPointerTy());
2816 }
2817
2818 // Insert node "GP copy globalreg" before call to function.
2819 // Lazy-binding stubs require GP to point to the GOT.
2820 if (IsPICCall) {
2821 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2822 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2823 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
2824 }
2825
2826 // Build a sequence of copy-to-reg nodes chained together with token
2827 // chain and flag operands which copy the outgoing args into registers.
2828 // The InFlag in necessary since all emitted instructions must be
2829 // stuck together.
2830 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2831 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2832 RegsToPass[i].second, InFlag);
2833 InFlag = Chain.getValue(1);
2834 }
2835
2836 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
2837 // = Chain, Callee, Reg#1, Reg#2, ...
2838 //
2839 // Returns a chain & a flag for retval copy to use.
2840 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2841 SmallVector<SDValue, 8> Ops;
2842 Ops.push_back(Chain);
2843 Ops.push_back(Callee);
2844
2845 // Add argument registers to the end of the list so that they are
2846 // known live into the call.
2847 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2848 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2849 RegsToPass[i].second.getValueType()));
2850
2851 // Add T9 register operand.
2852 if (T9.getNode())
2853 Ops.push_back(T9);
2854
2855 // Add a register mask operand representing the call-preserved registers.
2856 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2857 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2858 assert(Mask && "Missing call preserved mask for calling convention");
2859 Ops.push_back(DAG.getRegisterMask(Mask));
2860
2861 if (InFlag.getNode())
2862 Ops.push_back(InFlag);
2863
2864 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
2865 InFlag = Chain.getValue(1);
2866
2867 // Create the CALLSEQ_END node.
2868 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2869 DAG.getIntPtrConstant(0, true), InFlag);
2870 InFlag = Chain.getValue(1);
2871
2872 // Handle result values, copying them out of physregs into vregs that we
2873 // return.
2874 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2875 Ins, dl, DAG, InVals);
2876 }
2877
2878 /// LowerCallResult - Lower the result values of a call into the
2879 /// appropriate copies out of appropriate physical registers.
2880 SDValue
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2881 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2882 CallingConv::ID CallConv, bool isVarArg,
2883 const SmallVectorImpl<ISD::InputArg> &Ins,
2884 DebugLoc dl, SelectionDAG &DAG,
2885 SmallVectorImpl<SDValue> &InVals) const {
2886 // Assign locations to each value returned by this call.
2887 SmallVector<CCValAssign, 16> RVLocs;
2888 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2889 getTargetMachine(), RVLocs, *DAG.getContext());
2890
2891 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
2892
2893 // Copy all of the result registers out of their specified physreg.
2894 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2895 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
2896 RVLocs[i].getValVT(), InFlag).getValue(1);
2897 InFlag = Chain.getValue(2);
2898 InVals.push_back(Chain.getValue(0));
2899 }
2900
2901 return Chain;
2902 }
2903
2904 //===----------------------------------------------------------------------===//
2905 // Formal Arguments Calling Convention Implementation
2906 //===----------------------------------------------------------------------===//
ReadByValArg(MachineFunction & MF,SDValue Chain,DebugLoc dl,std::vector<SDValue> & OutChains,SelectionDAG & DAG,unsigned NumWords,SDValue FIN,const CCValAssign & VA,const ISD::ArgFlagsTy & Flags,const Argument * FuncArg)2907 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2908 std::vector<SDValue> &OutChains,
2909 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
2910 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
2911 const Argument *FuncArg) {
2912 unsigned LocMem = VA.getLocMemOffset();
2913 unsigned FirstWord = LocMem / 4;
2914
2915 // copy register A0 - A3 to frame object
2916 for (unsigned i = 0; i < NumWords; ++i) {
2917 unsigned CurWord = FirstWord + i;
2918 if (CurWord >= O32IntRegsSize)
2919 break;
2920
2921 unsigned SrcReg = O32IntRegs[CurWord];
2922 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
2923 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2924 DAG.getConstant(i * 4, MVT::i32));
2925 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
2926 StorePtr, MachinePointerInfo(FuncArg, i * 4),
2927 false, false, 0);
2928 OutChains.push_back(Store);
2929 }
2930 }
2931
2932 // Create frame object on stack and copy registers used for byval passing to it.
2933 static unsigned
CopyMips64ByValRegs(MachineFunction & MF,SDValue Chain,DebugLoc dl,std::vector<SDValue> & OutChains,SelectionDAG & DAG,const CCValAssign & VA,const ISD::ArgFlagsTy & Flags,MachineFrameInfo * MFI,bool IsRegLoc,SmallVectorImpl<SDValue> & InVals,MipsFunctionInfo * MipsFI,EVT PtrTy,const Argument * FuncArg)2934 CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2935 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
2936 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
2937 MachineFrameInfo *MFI, bool IsRegLoc,
2938 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
2939 EVT PtrTy, const Argument *FuncArg) {
2940 const uint16_t *Reg = Mips64IntRegs + 8;
2941 int FOOffset; // Frame object offset from virtual frame pointer.
2942
2943 if (IsRegLoc) {
2944 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
2945 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
2946 }
2947 else
2948 FOOffset = VA.getLocMemOffset();
2949
2950 // Create frame object.
2951 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
2952 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
2953 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
2954 InVals.push_back(FIN);
2955
2956 // Copy arg registers.
2957 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
2958 ++Reg, ++I) {
2959 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
2960 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
2961 DAG.getConstant(I * 8, PtrTy));
2962 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
2963 StorePtr, MachinePointerInfo(FuncArg, I * 8),
2964 false, false, 0);
2965 OutChains.push_back(Store);
2966 }
2967
2968 return LastFI;
2969 }
2970
2971 /// LowerFormalArguments - transform physical registers into virtual registers
2972 /// and generate load operations for arguments places on the stack.
2973 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2974 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2975 CallingConv::ID CallConv,
2976 bool isVarArg,
2977 const SmallVectorImpl<ISD::InputArg> &Ins,
2978 DebugLoc dl, SelectionDAG &DAG,
2979 SmallVectorImpl<SDValue> &InVals)
2980 const {
2981 MachineFunction &MF = DAG.getMachineFunction();
2982 MachineFrameInfo *MFI = MF.getFrameInfo();
2983 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2984
2985 MipsFI->setVarArgsFrameIndex(0);
2986
2987 // Used with vargs to acumulate store chains.
2988 std::vector<SDValue> OutChains;
2989
2990 // Assign locations to all of the incoming arguments.
2991 SmallVector<CCValAssign, 16> ArgLocs;
2992 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2993 getTargetMachine(), ArgLocs, *DAG.getContext());
2994
2995 if (CallConv == CallingConv::Fast)
2996 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC);
2997 else if (IsO32)
2998 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
2999 else
3000 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
3001
3002 Function::const_arg_iterator FuncArg =
3003 DAG.getMachineFunction().getFunction()->arg_begin();
3004 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
3005
3006 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
3007 CCValAssign &VA = ArgLocs[i];
3008 EVT ValVT = VA.getValVT();
3009 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3010 bool IsRegLoc = VA.isRegLoc();
3011
3012 if (Flags.isByVal()) {
3013 assert(Flags.getByValSize() &&
3014 "ByVal args of size 0 should have been ignored by front-end.");
3015 if (IsO32) {
3016 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
3017 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
3018 true);
3019 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3020 InVals.push_back(FIN);
3021 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
3022 &*FuncArg);
3023 } else // N32/64
3024 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
3025 MFI, IsRegLoc, InVals, MipsFI,
3026 getPointerTy(), &*FuncArg);
3027 continue;
3028 }
3029
3030 // Arguments stored on registers
3031 if (IsRegLoc) {
3032 EVT RegVT = VA.getLocVT();
3033 unsigned ArgReg = VA.getLocReg();
3034 const TargetRegisterClass *RC;
3035
3036 if (RegVT == MVT::i32)
3037 RC = &Mips::CPURegsRegClass;
3038 else if (RegVT == MVT::i64)
3039 RC = &Mips::CPU64RegsRegClass;
3040 else if (RegVT == MVT::f32)
3041 RC = &Mips::FGR32RegClass;
3042 else if (RegVT == MVT::f64)
3043 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3044 else
3045 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3046
3047 // Transform the arguments stored on
3048 // physical registers into virtual ones
3049 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3050 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3051
3052 // If this is an 8 or 16-bit value, it has been passed promoted
3053 // to 32 bits. Insert an assert[sz]ext to capture this, then
3054 // truncate to the right size.
3055 if (VA.getLocInfo() != CCValAssign::Full) {
3056 unsigned Opcode = 0;
3057 if (VA.getLocInfo() == CCValAssign::SExt)
3058 Opcode = ISD::AssertSext;
3059 else if (VA.getLocInfo() == CCValAssign::ZExt)
3060 Opcode = ISD::AssertZext;
3061 if (Opcode)
3062 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3063 DAG.getValueType(ValVT));
3064 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3065 }
3066
3067 // Handle floating point arguments passed in integer registers.
3068 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3069 (RegVT == MVT::i64 && ValVT == MVT::f64))
3070 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3071 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3072 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3073 getNextIntArgReg(ArgReg), RC);
3074 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3075 if (!Subtarget->isLittle())
3076 std::swap(ArgValue, ArgValue2);
3077 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3078 ArgValue, ArgValue2);
3079 }
3080
3081 InVals.push_back(ArgValue);
3082 } else { // VA.isRegLoc()
3083
3084 // sanity check
3085 assert(VA.isMemLoc());
3086
3087 // The stack pointer offset is relative to the caller stack frame.
3088 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3089 VA.getLocMemOffset(), true);
3090
3091 // Create load nodes to retrieve arguments from the stack
3092 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3093 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3094 MachinePointerInfo::getFixedStack(LastFI),
3095 false, false, false, 0));
3096 }
3097 }
3098
3099 // The mips ABIs for returning structs by value requires that we copy
3100 // the sret argument into $v0 for the return. Save the argument into
3101 // a virtual register so that we can access it from the return points.
3102 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3103 unsigned Reg = MipsFI->getSRetReturnReg();
3104 if (!Reg) {
3105 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
3106 MipsFI->setSRetReturnReg(Reg);
3107 }
3108 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3109 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3110 }
3111
3112 if (isVarArg) {
3113 unsigned NumOfRegs = IsO32 ? 4 : 8;
3114 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
3115 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
3116 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
3117 const TargetRegisterClass *RC = IsO32 ?
3118 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
3119 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
3120 unsigned RegSize = RC->getSize();
3121 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
3122
3123 // Offset of the first variable argument from stack pointer.
3124 int FirstVaArgOffset;
3125
3126 if (IsO32 || (Idx == NumOfRegs)) {
3127 FirstVaArgOffset =
3128 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
3129 } else
3130 FirstVaArgOffset = RegSlotOffset;
3131
3132 // Record the frame index of the first variable argument
3133 // which is a value necessary to VASTART.
3134 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
3135 MipsFI->setVarArgsFrameIndex(LastFI);
3136
3137 // Copy the integer registers that have not been used for argument passing
3138 // to the argument register save area. For O32, the save area is allocated
3139 // in the caller's stack frame, while for N32/64, it is allocated in the
3140 // callee's stack frame.
3141 for (int StackOffset = RegSlotOffset;
3142 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
3143 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
3144 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3145 MVT::getIntegerVT(RegSize * 8));
3146 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
3147 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
3148 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
3149 MachinePointerInfo(), false, false, 0));
3150 }
3151 }
3152
3153 MipsFI->setLastInArgFI(LastFI);
3154
3155 // All stores are grouped in one node to allow the matching between
3156 // the size of Ins and InVals. This only happens when on varg functions
3157 if (!OutChains.empty()) {
3158 OutChains.push_back(Chain);
3159 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3160 &OutChains[0], OutChains.size());
3161 }
3162
3163 return Chain;
3164 }
3165
3166 //===----------------------------------------------------------------------===//
3167 // Return Value Calling Convention Implementation
3168 //===----------------------------------------------------------------------===//
3169
3170 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,DebugLoc dl,SelectionDAG & DAG) const3171 MipsTargetLowering::LowerReturn(SDValue Chain,
3172 CallingConv::ID CallConv, bool isVarArg,
3173 const SmallVectorImpl<ISD::OutputArg> &Outs,
3174 const SmallVectorImpl<SDValue> &OutVals,
3175 DebugLoc dl, SelectionDAG &DAG) const {
3176
3177 // CCValAssign - represent the assignment of
3178 // the return value to a location
3179 SmallVector<CCValAssign, 16> RVLocs;
3180
3181 // CCState - Info about the registers and stack slot.
3182 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3183 getTargetMachine(), RVLocs, *DAG.getContext());
3184
3185 // Analize return values.
3186 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3187
3188 // If this is the first return lowered for this function, add
3189 // the regs to the liveout set for the function.
3190 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3191 for (unsigned i = 0; i != RVLocs.size(); ++i)
3192 if (RVLocs[i].isRegLoc())
3193 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3194 }
3195
3196 SDValue Flag;
3197
3198 // Copy the result values into the output registers.
3199 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3200 CCValAssign &VA = RVLocs[i];
3201 assert(VA.isRegLoc() && "Can only return in registers!");
3202
3203 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3204
3205 // guarantee that all emitted copies are
3206 // stuck together, avoiding something bad
3207 Flag = Chain.getValue(1);
3208 }
3209
3210 // The mips ABIs for returning structs by value requires that we copy
3211 // the sret argument into $v0 for the return. We saved the argument into
3212 // a virtual register in the entry block, so now we copy the value out
3213 // and into $v0.
3214 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3215 MachineFunction &MF = DAG.getMachineFunction();
3216 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3217 unsigned Reg = MipsFI->getSRetReturnReg();
3218
3219 if (!Reg)
3220 llvm_unreachable("sret virtual register not created in the entry block");
3221 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3222
3223 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
3224 Flag = Chain.getValue(1);
3225 }
3226
3227 // Return on Mips is always a "jr $ra"
3228 if (Flag.getNode())
3229 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3230
3231 // Return Void
3232 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
3233 }
3234
3235 //===----------------------------------------------------------------------===//
3236 // Mips Inline Assembly Support
3237 //===----------------------------------------------------------------------===//
3238
3239 /// getConstraintType - Given a constraint letter, return the type of
3240 /// constraint it is for this target.
3241 MipsTargetLowering::ConstraintType MipsTargetLowering::
getConstraintType(const std::string & Constraint) const3242 getConstraintType(const std::string &Constraint) const
3243 {
3244 // Mips specific constrainy
3245 // GCC config/mips/constraints.md
3246 //
3247 // 'd' : An address register. Equivalent to r
3248 // unless generating MIPS16 code.
3249 // 'y' : Equivalent to r; retained for
3250 // backwards compatibility.
3251 // 'c' : A register suitable for use in an indirect
3252 // jump. This will always be $25 for -mabicalls.
3253 // 'l' : The lo register. 1 word storage.
3254 // 'x' : The hilo register pair. Double word storage.
3255 if (Constraint.size() == 1) {
3256 switch (Constraint[0]) {
3257 default : break;
3258 case 'd':
3259 case 'y':
3260 case 'f':
3261 case 'c':
3262 case 'l':
3263 case 'x':
3264 return C_RegisterClass;
3265 }
3266 }
3267 return TargetLowering::getConstraintType(Constraint);
3268 }
3269
3270 /// Examine constraint type and operand type and determine a weight value.
3271 /// This object must already have been set up with the operand type
3272 /// and the current alternative constraint selected.
3273 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3274 MipsTargetLowering::getSingleConstraintMatchWeight(
3275 AsmOperandInfo &info, const char *constraint) const {
3276 ConstraintWeight weight = CW_Invalid;
3277 Value *CallOperandVal = info.CallOperandVal;
3278 // If we don't have a value, we can't do a match,
3279 // but allow it at the lowest weight.
3280 if (CallOperandVal == NULL)
3281 return CW_Default;
3282 Type *type = CallOperandVal->getType();
3283 // Look at the constraint type.
3284 switch (*constraint) {
3285 default:
3286 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3287 break;
3288 case 'd':
3289 case 'y':
3290 if (type->isIntegerTy())
3291 weight = CW_Register;
3292 break;
3293 case 'f':
3294 if (type->isFloatTy())
3295 weight = CW_Register;
3296 break;
3297 case 'c': // $25 for indirect jumps
3298 case 'l': // lo register
3299 case 'x': // hilo register pair
3300 if (type->isIntegerTy())
3301 weight = CW_SpecificReg;
3302 break;
3303 case 'I': // signed 16 bit immediate
3304 case 'J': // integer zero
3305 case 'K': // unsigned 16 bit immediate
3306 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3307 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3308 case 'O': // signed 15 bit immediate (+- 16383)
3309 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3310 if (isa<ConstantInt>(CallOperandVal))
3311 weight = CW_Constant;
3312 break;
3313 }
3314 return weight;
3315 }
3316
3317 /// Given a register class constraint, like 'r', if this corresponds directly
3318 /// to an LLVM register class, return a register of 0 and the register class
3319 /// pointer.
3320 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
getRegForInlineAsmConstraint(const std::string & Constraint,EVT VT) const3321 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3322 {
3323 if (Constraint.size() == 1) {
3324 switch (Constraint[0]) {
3325 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3326 case 'y': // Same as 'r'. Exists for compatibility.
3327 case 'r':
3328 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3329 return std::make_pair(0U, &Mips::CPURegsRegClass);
3330 if (VT == MVT::i64 && !HasMips64)
3331 return std::make_pair(0U, &Mips::CPURegsRegClass);
3332 if (VT == MVT::i64 && HasMips64)
3333 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3334 // This will generate an error message
3335 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3336 case 'f':
3337 if (VT == MVT::f32)
3338 return std::make_pair(0U, &Mips::FGR32RegClass);
3339 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3340 if (Subtarget->isFP64bit())
3341 return std::make_pair(0U, &Mips::FGR64RegClass);
3342 return std::make_pair(0U, &Mips::AFGR64RegClass);
3343 }
3344 break;
3345 case 'c': // register suitable for indirect jump
3346 if (VT == MVT::i32)
3347 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3348 assert(VT == MVT::i64 && "Unexpected type.");
3349 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3350 case 'l': // register suitable for indirect jump
3351 if (VT == MVT::i32)
3352 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3353 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3354 case 'x': // register suitable for indirect jump
3355 // Fixme: Not triggering the use of both hi and low
3356 // This will generate an error message
3357 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3358 }
3359 }
3360 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3361 }
3362
3363 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3364 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3365 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3366 std::string &Constraint,
3367 std::vector<SDValue>&Ops,
3368 SelectionDAG &DAG) const {
3369 SDValue Result(0, 0);
3370
3371 // Only support length 1 constraints for now.
3372 if (Constraint.length() > 1) return;
3373
3374 char ConstraintLetter = Constraint[0];
3375 switch (ConstraintLetter) {
3376 default: break; // This will fall through to the generic implementation
3377 case 'I': // Signed 16 bit constant
3378 // If this fails, the parent routine will give an error
3379 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3380 EVT Type = Op.getValueType();
3381 int64_t Val = C->getSExtValue();
3382 if (isInt<16>(Val)) {
3383 Result = DAG.getTargetConstant(Val, Type);
3384 break;
3385 }
3386 }
3387 return;
3388 case 'J': // integer zero
3389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3390 EVT Type = Op.getValueType();
3391 int64_t Val = C->getZExtValue();
3392 if (Val == 0) {
3393 Result = DAG.getTargetConstant(0, Type);
3394 break;
3395 }
3396 }
3397 return;
3398 case 'K': // unsigned 16 bit immediate
3399 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3400 EVT Type = Op.getValueType();
3401 uint64_t Val = (uint64_t)C->getZExtValue();
3402 if (isUInt<16>(Val)) {
3403 Result = DAG.getTargetConstant(Val, Type);
3404 break;
3405 }
3406 }
3407 return;
3408 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3409 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3410 EVT Type = Op.getValueType();
3411 int64_t Val = C->getSExtValue();
3412 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3413 Result = DAG.getTargetConstant(Val, Type);
3414 break;
3415 }
3416 }
3417 return;
3418 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3419 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3420 EVT Type = Op.getValueType();
3421 int64_t Val = C->getSExtValue();
3422 if ((Val >= -65535) && (Val <= -1)) {
3423 Result = DAG.getTargetConstant(Val, Type);
3424 break;
3425 }
3426 }
3427 return;
3428 case 'O': // signed 15 bit immediate
3429 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3430 EVT Type = Op.getValueType();
3431 int64_t Val = C->getSExtValue();
3432 if ((isInt<15>(Val))) {
3433 Result = DAG.getTargetConstant(Val, Type);
3434 break;
3435 }
3436 }
3437 return;
3438 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3440 EVT Type = Op.getValueType();
3441 int64_t Val = C->getSExtValue();
3442 if ((Val <= 65535) && (Val >= 1)) {
3443 Result = DAG.getTargetConstant(Val, Type);
3444 break;
3445 }
3446 }
3447 return;
3448 }
3449
3450 if (Result.getNode()) {
3451 Ops.push_back(Result);
3452 return;
3453 }
3454
3455 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3456 }
3457
3458 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3459 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3460 // The Mips target isn't yet aware of offsets.
3461 return false;
3462 }
3463
getOptimalMemOpType(uint64_t Size,unsigned DstAlign,unsigned SrcAlign,bool IsZeroVal,bool MemcpyStrSrc,MachineFunction & MF) const3464 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3465 unsigned SrcAlign, bool IsZeroVal,
3466 bool MemcpyStrSrc,
3467 MachineFunction &MF) const {
3468 if (Subtarget->hasMips64())
3469 return MVT::i64;
3470
3471 return MVT::i32;
3472 }
3473
isFPImmLegal(const APFloat & Imm,EVT VT) const3474 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3475 if (VT != MVT::f32 && VT != MVT::f64)
3476 return false;
3477 if (Imm.isNegZero())
3478 return false;
3479 return Imm.isZero();
3480 }
3481
getJumpTableEncoding() const3482 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3483 if (IsN64)
3484 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3485
3486 return TargetLowering::getJumpTableEncoding();
3487 }
3488