1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef MIPSSEINSTRUCTIONINFO_H 15 #define MIPSSEINSTRUCTIONINFO_H 16 17 #include "MipsInstrInfo.h" 18 #include "MipsSERegisterInfo.h" 19 20 namespace llvm { 21 22 class MipsSEInstrInfo : public MipsInstrInfo { 23 const MipsSERegisterInfo RI; 24 bool IsN64; 25 26 public: 27 explicit MipsSEInstrInfo(MipsTargetMachine &TM); 28 29 virtual const MipsRegisterInfo &getRegisterInfo() const; 30 31 /// isLoadFromStackSlot - If the specified machine instruction is a direct 32 /// load from a stack slot, return the virtual or physical register number of 33 /// the destination along with the FrameIndex of the loaded stack slot. If 34 /// not, return 0. This predicate must return 0 if the instruction has 35 /// any side effects other than loading from the stack slot. 36 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 37 int &FrameIndex) const; 38 39 /// isStoreToStackSlot - If the specified machine instruction is a direct 40 /// store to a stack slot, return the virtual or physical register number of 41 /// the source reg along with the FrameIndex of the loaded stack slot. If 42 /// not, return 0. This predicate must return 0 if the instruction has 43 /// any side effects other than storing to the stack slot. 44 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 45 int &FrameIndex) const; 46 47 virtual void copyPhysReg(MachineBasicBlock &MBB, 48 MachineBasicBlock::iterator MI, DebugLoc DL, 49 unsigned DestReg, unsigned SrcReg, 50 bool KillSrc) const; 51 52 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 53 MachineBasicBlock::iterator MBBI, 54 unsigned SrcReg, bool isKill, int FrameIndex, 55 const TargetRegisterClass *RC, 56 const TargetRegisterInfo *TRI) const; 57 58 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 59 MachineBasicBlock::iterator MBBI, 60 unsigned DestReg, int FrameIndex, 61 const TargetRegisterClass *RC, 62 const TargetRegisterInfo *TRI) const; 63 64 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 65 66 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 67 68 /// Adjust SP by Amount bytes. 69 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 70 MachineBasicBlock::iterator I) const; 71 72 /// Emit a series of instructions to load an immediate. If NewImm is a 73 /// non-NULL parameter, the last instruction is not emitted, but instead 74 /// its immediate operand is returned in NewImm. 75 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator II, DebugLoc DL, 77 unsigned *NewImm) const; 78 79 private: 80 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 81 82 void ExpandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 83 unsigned Opc) const; 84 void ExpandExtractElementF64(MachineBasicBlock &MBB, 85 MachineBasicBlock::iterator I) const; 86 void ExpandBuildPairF64(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator I) const; 88 }; 89 90 } 91 92 #endif 93