1; RUN: opt -insert-edge-profiling -o %t1 < %s 2; RUN: rm -f %t1.prof_data 3; RUN: lli -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ 4; RUN: -llvmprof-output %t1.prof_data 5; RUN: opt -profile-file %t1.prof_data -profile-metadata-loader -S -o - < %s \ 6; RUN: | FileCheck %s 7; RUN: rm -f %t1.prof_data 8 9; FIXME: profile_rt.dll could be built on win32. 10; REQUIRES: loadable_module 11 12;; func_switch - Test branch probabilities for a switch instruction with an 13;; even chance of taking each case (or no case). 14define i32 @func_switch(i32 %N) nounwind uwtable { 15entry: 16 %retval = alloca i32, align 4 17 %N.addr = alloca i32, align 4 18 store i32 %N, i32* %N.addr, align 4 19 %0 = load i32* %N.addr, align 4 20 %rem = srem i32 %0, 4 21 switch i32 %rem, label %sw.epilog [ 22 i32 0, label %sw.bb 23 i32 1, label %sw.bb1 24 i32 2, label %sw.bb2 25 ] 26; CHECK: ], !prof !0 27 28sw.bb: 29 store i32 5, i32* %retval 30 br label %return 31 32sw.bb1: 33 store i32 6, i32* %retval 34 br label %return 35 36sw.bb2: 37 store i32 7, i32* %retval 38 br label %return 39 40sw.epilog: 41 store i32 8, i32* %retval 42 br label %return 43 44return: 45 %1 = load i32* %retval 46 ret i32 %1 47} 48 49;; func_switch_switch - Test branch probabilities in a switch-instruction that 50;; leads to further switch instructions. The first-tier switch occludes some 51;; possibilities in the second-tier switches, leading to some branches having a 52;; 0 probability. 53define i32 @func_switch_switch(i32 %N) nounwind uwtable { 54entry: 55 %retval = alloca i32, align 4 56 %N.addr = alloca i32, align 4 57 store i32 %N, i32* %N.addr, align 4 58 %0 = load i32* %N.addr, align 4 59 %rem = srem i32 %0, 2 60 switch i32 %rem, label %sw.default11 [ 61 i32 0, label %sw.bb 62 i32 1, label %sw.bb5 63 ] 64; CHECK: ], !prof !1 65 66sw.bb: 67 %1 = load i32* %N.addr, align 4 68 %rem1 = srem i32 %1, 4 69 switch i32 %rem1, label %sw.default [ 70 i32 0, label %sw.bb2 71 i32 1, label %sw.bb3 72 i32 2, label %sw.bb4 73 ] 74; CHECK: ], !prof !2 75 76sw.bb2: 77 store i32 5, i32* %retval 78 br label %return 79 80sw.bb3: 81 store i32 6, i32* %retval 82 br label %return 83 84sw.bb4: 85 store i32 7, i32* %retval 86 br label %return 87 88sw.default: 89 store i32 8, i32* %retval 90 br label %return 91 92sw.bb5: 93 %2 = load i32* %N.addr, align 4 94 %rem6 = srem i32 %2, 4 95 switch i32 %rem6, label %sw.default10 [ 96 i32 0, label %sw.bb7 97 i32 1, label %sw.bb8 98 i32 2, label %sw.bb9 99 ] 100; CHECK: ], !prof !3 101 102sw.bb7: 103 store i32 9, i32* %retval 104 br label %return 105 106sw.bb8: 107 store i32 10, i32* %retval 108 br label %return 109 110sw.bb9: 111 store i32 11, i32* %retval 112 br label %return 113 114sw.default10: 115 store i32 12, i32* %retval 116 br label %return 117 118sw.default11: 119 store i32 13, i32* %retval 120 br label %return 121 122return: 123 %3 = load i32* %retval 124 ret i32 %3 125} 126 127define i32 @main(i32 %argc, i8** %argv) nounwind uwtable { 128entry: 129 %retval = alloca i32, align 4 130 %argc.addr = alloca i32, align 4 131 %argv.addr = alloca i8**, align 8 132 %loop = alloca i32, align 4 133 store i32 0, i32* %retval 134 store i32 0, i32* %loop, align 4 135 br label %for.cond 136 137for.cond: 138 %0 = load i32* %loop, align 4 139 %cmp = icmp slt i32 %0, 4000 140 br i1 %cmp, label %for.body, label %for.end 141; CHECK: br i1 %cmp, label %for.body, label %for.end, !prof !4 142 143for.body: 144 %1 = load i32* %loop, align 4 145 %call = call i32 @func_switch(i32 %1) 146 %2 = load i32* %loop, align 4 147 %call1 = call i32 @func_switch_switch(i32 %2) 148 br label %for.inc 149 150for.inc: 151 %3 = load i32* %loop, align 4 152 %inc = add nsw i32 %3, 1 153 store i32 %inc, i32* %loop, align 4 154 br label %for.cond 155 156for.end: 157 ret i32 0 158} 159 160; CHECK: !0 = metadata !{metadata !"branch_weights", i32 1000, i32 1000, i32 1000, i32 1000} 161; CHECK: !1 = metadata !{metadata !"branch_weights", i32 0, i32 2000, i32 2000} 162; CHECK: !2 = metadata !{metadata !"branch_weights", i32 0, i32 1000, i32 0, i32 1000} 163; CHECK: !3 = metadata !{metadata !"branch_weights", i32 1000, i32 0, i32 1000, i32 0} 164; CHECK: !4 = metadata !{metadata !"branch_weights", i32 4000, i32 1} 165; CHECK-NOT: !5 166