1; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s 2; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s 3; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s 4; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s 5 6 7define i16 @cvt_i16_f32(float %x) { 8; CHECK: cvt.rzi.u16.f32 %rs{{[0-9]+}}, %f{{[0-9]+}}; 9; CHECK: ret; 10 %a = fptoui float %x to i16 11 ret i16 %a 12} 13 14define i16 @cvt_i16_f64(double %x) { 15; CHECK: cvt.rzi.u16.f64 %rs{{[0-9]+}}, %fl{{[0-9]+}}; 16; CHECK: ret; 17 %a = fptoui double %x to i16 18 ret i16 %a 19} 20 21define i32 @cvt_i32_f32(float %x) { 22; CHECK: cvt.rzi.u32.f32 %r{{[0-9]+}}, %f{{[0-9]+}}; 23; CHECK: ret; 24 %a = fptoui float %x to i32 25 ret i32 %a 26} 27 28define i32 @cvt_i32_f64(double %x) { 29; CHECK: cvt.rzi.u32.f64 %r{{[0-9]+}}, %fl{{[0-9]+}}; 30; CHECK: ret; 31 %a = fptoui double %x to i32 32 ret i32 %a 33} 34 35 36define i64 @cvt_i64_f32(float %x) { 37; CHECK: cvt.rzi.u64.f32 %rl{{[0-9]+}}, %f{{[0-9]+}}; 38; CHECK: ret; 39 %a = fptoui float %x to i64 40 ret i64 %a 41} 42 43define i64 @cvt_i64_f64(double %x) { 44; CHECK: cvt.rzi.u64.f64 %rl{{[0-9]+}}, %fl{{[0-9]+}}; 45; CHECK: ret; 46 %a = fptoui double %x to i64 47 ret i64 %a 48} 49 50define float @cvt_f32_i16(i16 %x) { 51; CHECK: cvt.rn.f32.u16 %f{{[0-9]+}}, %rs{{[0-9]+}}; 52; CHECK: ret; 53 %a = uitofp i16 %x to float 54 ret float %a 55} 56 57define float @cvt_f32_i32(i32 %x) { 58; CHECK: cvt.rn.f32.u32 %f{{[0-9]+}}, %r{{[0-9]+}}; 59; CHECK: ret; 60 %a = uitofp i32 %x to float 61 ret float %a 62} 63 64define float @cvt_f32_i64(i64 %x) { 65; CHECK: cvt.rn.f32.u64 %f{{[0-9]+}}, %rl{{[0-9]+}}; 66; CHECK: ret; 67 %a = uitofp i64 %x to float 68 ret float %a 69} 70 71define float @cvt_f32_f64(double %x) { 72; CHECK: cvt.rn.f32.f64 %f{{[0-9]+}}, %fl{{[0-9]+}}; 73; CHECK: ret; 74 %a = fptrunc double %x to float 75 ret float %a 76} 77 78define float @cvt_f32_s16(i16 %x) { 79; CHECK: cvt.rn.f32.s16 %f{{[0-9]+}}, %rs{{[0-9]+}} 80; CHECK: ret 81 %a = sitofp i16 %x to float 82 ret float %a 83} 84 85define float @cvt_f32_s32(i32 %x) { 86; CHECK: cvt.rn.f32.s32 %f{{[0-9]+}}, %r{{[0-9]+}} 87; CHECK: ret 88 %a = sitofp i32 %x to float 89 ret float %a 90} 91 92define float @cvt_f32_s64(i64 %x) { 93; CHECK: cvt.rn.f32.s64 %f{{[0-9]+}}, %rl{{[0-9]+}} 94; CHECK: ret 95 %a = sitofp i64 %x to float 96 ret float %a 97} 98 99define double @cvt_f64_i16(i16 %x) { 100; CHECK: cvt.rn.f64.u16 %fl{{[0-9]+}}, %rs{{[0-9]+}}; 101; CHECK: ret; 102 %a = uitofp i16 %x to double 103 ret double %a 104} 105 106define double @cvt_f64_i32(i32 %x) { 107; CHECK: cvt.rn.f64.u32 %fl{{[0-9]+}}, %r{{[0-9]+}}; 108; CHECK: ret; 109 %a = uitofp i32 %x to double 110 ret double %a 111} 112 113define double @cvt_f64_i64(i64 %x) { 114; CHECK: cvt.rn.f64.u64 %fl{{[0-9]+}}, %rl{{[0-9]+}}; 115; CHECK: ret; 116 %a = uitofp i64 %x to double 117 ret double %a 118} 119 120define double @cvt_f64_f32(float %x) { 121; CHECK: cvt.f64.f32 %fl{{[0-9]+}}, %f{{[0-9]+}}; 122; CHECK: ret; 123 %a = fpext float %x to double 124 ret double %a 125} 126 127define double @cvt_f64_s16(i16 %x) { 128; CHECK: cvt.rn.f64.s16 %fl{{[0-9]+}}, %rs{{[0-9]+}} 129; CHECK: ret 130 %a = sitofp i16 %x to double 131 ret double %a 132} 133 134define double @cvt_f64_s32(i32 %x) { 135; CHECK: cvt.rn.f64.s32 %fl{{[0-9]+}}, %r{{[0-9]+}} 136; CHECK: ret 137 %a = sitofp i32 %x to double 138 ret double %a 139} 140 141define double @cvt_f64_s64(i64 %x) { 142; CHECK: cvt.rn.f64.s64 %fl{{[0-9]+}}, %rl{{[0-9]+}} 143; CHECK: ret 144 %a = sitofp i64 %x to double 145 ret double %a 146} 147