1; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s 2 3define i64 @test1(i32 %xx, i32 %test) nounwind { 4 %conv = zext i32 %xx to i64 5 %and = and i32 %test, 7 6 %sh_prom = zext i32 %and to i64 7 %shl = shl i64 %conv, %sh_prom 8 ret i64 %shl 9; CHECK: test1: 10; CHECK: shll %cl, %eax 11; CHECK: shrl %edx 12; CHECK: xorb $31 13; CHECK: shrl %cl, %edx 14} 15 16define i64 @test2(i64 %xx, i32 %test) nounwind { 17 %and = and i32 %test, 7 18 %sh_prom = zext i32 %and to i64 19 %shl = shl i64 %xx, %sh_prom 20 ret i64 %shl 21; CHECK: test2: 22; CHECK: shll %cl, %esi 23; CHECK: shrl %edx 24; CHECK: xorb $31 25; CHECK: shrl %cl, %edx 26; CHECK: orl %esi, %edx 27; CHECK: shll %cl, %eax 28} 29 30define i64 @test3(i64 %xx, i32 %test) nounwind { 31 %and = and i32 %test, 7 32 %sh_prom = zext i32 %and to i64 33 %shr = lshr i64 %xx, %sh_prom 34 ret i64 %shr 35; CHECK: test3: 36; CHECK: shrl %cl, %esi 37; CHECK: leal (%edx,%edx), %eax 38; CHECK: xorb $31, %cl 39; CHECK: shll %cl, %eax 40; CHECK: orl %esi, %eax 41; CHECK: shrl %cl, %edx 42} 43 44define i64 @test4(i64 %xx, i32 %test) nounwind { 45 %and = and i32 %test, 7 46 %sh_prom = zext i32 %and to i64 47 %shr = ashr i64 %xx, %sh_prom 48 ret i64 %shr 49; CHECK: test4: 50; CHECK: shrl %cl, %esi 51; CHECK: leal (%edx,%edx), %eax 52; CHECK: xorb $31, %cl 53; CHECK: shll %cl, %eax 54; CHECK: orl %esi, %eax 55; CHECK: sarl %cl, %edx 56} 57