1 /*
2 * MIPS CPU interrupt support.
3 *
4 */
5
6 #include "hw.h"
7
8 /* Stub functions for hardware that don't exist. */
pic_info(void)9 void pic_info(void)
10 {
11 }
12
irq_info(void)13 void irq_info(void)
14 {
15 }
16
mips_cpu_irq_handler(void * opaque,int irq,int level)17 static void mips_cpu_irq_handler(void *opaque, int irq, int level)
18 {
19 CPUState *env = (CPUState *)opaque;
20 int causebit;
21
22 if (irq < 0 || 7 < irq)
23 cpu_abort(env, "mips_pic_cpu_handler: Bad interrupt line %d\n",
24 irq);
25
26 causebit = 0x00000100 << irq;
27 if (level) {
28 env->CP0_Cause |= causebit;
29 cpu_interrupt(env, CPU_INTERRUPT_HARD);
30 } else {
31 env->CP0_Cause &= ~causebit;
32 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
33 }
34 }
35
mips_cpu_irq_init(CPUState * env)36 qemu_irq *mips_cpu_irq_init(CPUState *env)
37 {
38 return qemu_allocate_irqs(mips_cpu_irq_handler, env, 8);
39 }
40