1 /*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #include <errno.h>
17 #include <fcntl.h>
18 #include <math.h>
19 #include <poll.h>
20 #include <pthread.h>
21 #include <stdio.h>
22 #include <stdlib.h>
23
24 #include <sys/ioctl.h>
25 #include <sys/mman.h>
26 #include <sys/time.h>
27 #include <sys/resource.h>
28
29 #include <s3c-fb.h>
30
31 #include <EGL/egl.h>
32
33 #define HWC_REMOVE_DEPRECATED_VERSIONS 1
34
35 #include <cutils/compiler.h>
36 #include <cutils/log.h>
37 #include <cutils/properties.h>
38 #include <hardware/gralloc.h>
39 #include <hardware/hardware.h>
40 #include <hardware/hwcomposer.h>
41 #include <hardware_legacy/uevent.h>
42 #include <utils/String8.h>
43 #include <utils/Vector.h>
44
45 #include <sync/sync.h>
46
47 #include "ion.h"
48 #include "gralloc_priv.h"
49 #include "exynos_gscaler.h"
50 #include "exynos_format.h"
51 #include "exynos_v4l2.h"
52 #include "s5p_tvout_v4l2.h"
53
54 const size_t NUM_HW_WINDOWS = 5;
55 const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1;
56 const size_t MAX_PIXELS = 2560 * 1600 * 2;
57 const size_t GSC_W_ALIGNMENT = 16;
58 const size_t GSC_H_ALIGNMENT = 16;
59 const size_t GSC_DST_CROP_W_ALIGNMENT_RGB888 = 32;
60 const size_t GSC_DST_W_ALIGNMENT_RGB888 = 32;
61 const size_t GSC_DST_H_ALIGNMENT_RGB888 = 1;
62 const size_t FIMD_GSC_IDX = 0;
63 const size_t HDMI_GSC_IDX = 1;
64 const int AVAILABLE_GSC_UNITS[] = { 0, 3 };
65 const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) /
66 sizeof(AVAILABLE_GSC_UNITS[0]);
67 const size_t BURSTLEN_BYTES = 16 * 8;
68 const size_t NUM_HDMI_BUFFERS = 3;
69
70 struct exynos5_hwc_composer_device_1_t;
71
72 struct exynos5_gsc_map_t {
73 enum {
74 GSC_NONE = 0,
75 GSC_M2M,
76 // TODO: GSC_LOCAL_PATH
77 } mode;
78 int idx;
79 };
80
81 struct exynos5_hwc_post_data_t {
82 int overlay_map[NUM_HW_WINDOWS];
83 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS];
84 size_t fb_window;
85 };
86
87 const size_t NUM_GSC_DST_BUFS = 3;
88 struct exynos5_gsc_data_t {
89 void *gsc;
90 exynos_gsc_img src_cfg;
91 exynos_gsc_img dst_cfg;
92 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS];
93 int dst_buf_fence[NUM_GSC_DST_BUFS];
94 size_t current_buf;
95 };
96
97 struct hdmi_layer_t {
98 int id;
99 int fd;
100 bool enabled;
101 exynos_gsc_img cfg;
102
103 bool streaming;
104 size_t current_buf;
105 size_t queued_buf;
106 };
107
108 struct exynos5_hwc_composer_device_1_t {
109 hwc_composer_device_1_t base;
110
111 int fd;
112 int vsync_fd;
113 exynos5_hwc_post_data_t bufs;
114
115 const private_module_t *gralloc_module;
116 alloc_device_t *alloc_device;
117 const hwc_procs_t *procs;
118 pthread_t vsync_thread;
119 int force_gpu;
120
121 int32_t xres;
122 int32_t yres;
123 int32_t xdpi;
124 int32_t ydpi;
125 int32_t vsync_period;
126
127 int hdmi_mixer0;
128 bool hdmi_hpd;
129 bool hdmi_enabled;
130 bool hdmi_blanked;
131 bool hdmi_fb_needed;
132 int hdmi_w;
133 int hdmi_h;
134
135 hdmi_layer_t hdmi_layers[2];
136
137 exynos5_gsc_data_t gsc[NUM_GSC_UNITS];
138
139 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS];
140 size_t last_fb_window;
141 const void *last_handles[NUM_HW_WINDOWS];
142 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS];
143 };
144
145 static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev,
146 size_t gsc_idx);
147
dump_handle(private_handle_t * h)148 static void dump_handle(private_handle_t *h)
149 {
150 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u",
151 h->format, h->width, h->height, h->stride, h->vstride);
152 }
153
dump_layer(hwc_layer_1_t const * l)154 static void dump_layer(hwc_layer_1_t const *l)
155 {
156 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, "
157 "{%d,%d,%d,%d}, {%d,%d,%d,%d}",
158 l->compositionType, l->flags, l->handle, l->transform,
159 l->blending,
160 l->sourceCrop.left,
161 l->sourceCrop.top,
162 l->sourceCrop.right,
163 l->sourceCrop.bottom,
164 l->displayFrame.left,
165 l->displayFrame.top,
166 l->displayFrame.right,
167 l->displayFrame.bottom);
168
169 if(l->handle && !(l->flags & HWC_SKIP_LAYER))
170 dump_handle(private_handle_t::dynamicCast(l->handle));
171 }
172
dump_config(s3c_fb_win_config & c)173 static void dump_config(s3c_fb_win_config &c)
174 {
175 ALOGV("\tstate = %u", c.state);
176 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) {
177 ALOGV("\t\tfd = %d, offset = %u, stride = %u, "
178 "x = %d, y = %d, w = %u, h = %u, "
179 "format = %u, blending = %u",
180 c.fd, c.offset, c.stride,
181 c.x, c.y, c.w, c.h,
182 c.format, c.blending);
183 }
184 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) {
185 ALOGV("\t\tcolor = %u", c.color);
186 }
187 }
188
dump_gsc_img(exynos_gsc_img & c)189 static void dump_gsc_img(exynos_gsc_img &c)
190 {
191 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u",
192 c.x, c.y, c.w, c.h, c.fw, c.fh);
193 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u",
194 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode);
195 }
196
WIDTH(const hwc_rect & rect)197 inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; }
HEIGHT(const hwc_rect & rect)198 inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; }
max(T a,T b)199 template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; }
min(T a,T b)200 template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; }
201
align_crop_and_center(T & w,T & h,hwc_rect_t * crop,size_t alignment)202 template<typename T> void align_crop_and_center(T &w, T &h,
203 hwc_rect_t *crop, size_t alignment)
204 {
205 double aspect = 1.0 * h / w;
206 T w_orig = w, h_orig = h;
207
208 w = ALIGN(w, alignment);
209 h = round(aspect * w);
210 if (crop) {
211 crop->left = (w - w_orig) / 2;
212 crop->top = (h - h_orig) / 2;
213 crop->right = crop->left + w_orig;
214 crop->bottom = crop->top + h_orig;
215 }
216 }
217
is_transformed(const hwc_layer_1_t & layer)218 static bool is_transformed(const hwc_layer_1_t &layer)
219 {
220 return layer.transform != 0;
221 }
222
is_rotated(const hwc_layer_1_t & layer)223 static bool is_rotated(const hwc_layer_1_t &layer)
224 {
225 return (layer.transform & HAL_TRANSFORM_ROT_90) ||
226 (layer.transform & HAL_TRANSFORM_ROT_180);
227 }
228
is_scaled(const hwc_layer_1_t & layer)229 static bool is_scaled(const hwc_layer_1_t &layer)
230 {
231 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) ||
232 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop);
233 }
234
gsc_dst_cfg_changed(exynos_gsc_img & c1,exynos_gsc_img & c2)235 static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2)
236 {
237 return c1.x != c2.x ||
238 c1.y != c2.y ||
239 c1.w != c2.w ||
240 c1.h != c2.h ||
241 c1.format != c2.format ||
242 c1.rot != c2.rot ||
243 c1.cacheable != c2.cacheable ||
244 c1.drmMode != c2.drmMode;
245 }
246
gsc_src_cfg_changed(exynos_gsc_img & c1,exynos_gsc_img & c2)247 static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2)
248 {
249 return gsc_dst_cfg_changed(c1, c2) ||
250 c1.fw != c2.fw ||
251 c1.fh != c2.fh;
252 }
253
exynos5_format_to_s3c_format(int format)254 static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format)
255 {
256 switch (format) {
257 case HAL_PIXEL_FORMAT_RGBA_8888:
258 return S3C_FB_PIXEL_FORMAT_RGBA_8888;
259 case HAL_PIXEL_FORMAT_RGBX_8888:
260 return S3C_FB_PIXEL_FORMAT_RGBX_8888;
261 case HAL_PIXEL_FORMAT_RGBA_5551:
262 return S3C_FB_PIXEL_FORMAT_RGBA_5551;
263 case HAL_PIXEL_FORMAT_RGB_565:
264 return S3C_FB_PIXEL_FORMAT_RGB_565;
265 case HAL_PIXEL_FORMAT_BGRA_8888:
266 return S3C_FB_PIXEL_FORMAT_BGRA_8888;
267 default:
268 return S3C_FB_PIXEL_FORMAT_MAX;
269 }
270 }
271
exynos5_format_is_supported(int format)272 static bool exynos5_format_is_supported(int format)
273 {
274 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX;
275 }
276
exynos5_format_is_rgb(int format)277 static bool exynos5_format_is_rgb(int format)
278 {
279 switch (format) {
280 case HAL_PIXEL_FORMAT_RGBA_8888:
281 case HAL_PIXEL_FORMAT_RGBX_8888:
282 case HAL_PIXEL_FORMAT_RGB_888:
283 case HAL_PIXEL_FORMAT_RGB_565:
284 case HAL_PIXEL_FORMAT_BGRA_8888:
285 case HAL_PIXEL_FORMAT_RGBA_5551:
286 case HAL_PIXEL_FORMAT_RGBA_4444:
287 return true;
288
289 default:
290 return false;
291 }
292 }
293
exynos5_format_is_supported_by_gscaler(int format)294 static bool exynos5_format_is_supported_by_gscaler(int format)
295 {
296 switch (format) {
297 case HAL_PIXEL_FORMAT_RGBX_8888:
298 case HAL_PIXEL_FORMAT_RGB_565:
299 case HAL_PIXEL_FORMAT_EXYNOS_YV12:
300 case HAL_PIXEL_FORMAT_YCbCr_420_SP:
301 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED:
302 return true;
303
304 default:
305 return false;
306 }
307 }
308
exynos5_format_is_ycrcb(int format)309 static bool exynos5_format_is_ycrcb(int format)
310 {
311 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12;
312 }
313
exynos5_format_requires_gscaler(int format)314 static bool exynos5_format_requires_gscaler(int format)
315 {
316 return (exynos5_format_is_supported_by_gscaler(format) &&
317 (format != HAL_PIXEL_FORMAT_RGBX_8888) && (format != HAL_PIXEL_FORMAT_RGB_565));
318 }
319
exynos5_format_to_bpp(int format)320 static uint8_t exynos5_format_to_bpp(int format)
321 {
322 switch (format) {
323 case HAL_PIXEL_FORMAT_RGBA_8888:
324 case HAL_PIXEL_FORMAT_RGBX_8888:
325 case HAL_PIXEL_FORMAT_BGRA_8888:
326 return 32;
327
328 case HAL_PIXEL_FORMAT_RGBA_5551:
329 case HAL_PIXEL_FORMAT_RGBA_4444:
330 case HAL_PIXEL_FORMAT_RGB_565:
331 return 16;
332
333 default:
334 ALOGW("unrecognized pixel format %u", format);
335 return 0;
336 }
337 }
338
is_x_aligned(const hwc_layer_1_t & layer,int format)339 static bool is_x_aligned(const hwc_layer_1_t &layer, int format)
340 {
341 if (!exynos5_format_is_supported(format))
342 return true;
343
344 uint8_t bpp = exynos5_format_to_bpp(format);
345 uint8_t pixel_alignment = 32 / bpp;
346
347 return (layer.displayFrame.left % pixel_alignment) == 0 &&
348 (layer.displayFrame.right % pixel_alignment) == 0;
349 }
350
dst_crop_w_aligned(int dest_w)351 static bool dst_crop_w_aligned(int dest_w)
352 {
353 int dst_crop_w_alignement;
354
355 /* GSC's dst crop size should be aligned 128Bytes */
356 dst_crop_w_alignement = GSC_DST_CROP_W_ALIGNMENT_RGB888;
357
358 return (dest_w % dst_crop_w_alignement) == 0;
359 }
360
exynos5_supports_gscaler(hwc_layer_1_t & layer,int format,bool local_path)361 static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format,
362 bool local_path)
363 {
364 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle);
365
366 int max_w = is_rotated(layer) ? 2048 : 4800;
367 int max_h = is_rotated(layer) ? 2048 : 3344;
368
369 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90);
370 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 |
371 // HAL_TRANSFORM_ROT_180
372
373 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop);
374 int dest_w, dest_h;
375 if (rot90or270) {
376 dest_w = HEIGHT(layer.displayFrame);
377 dest_h = WIDTH(layer.displayFrame);
378 } else {
379 dest_w = WIDTH(layer.displayFrame);
380 dest_h = HEIGHT(layer.displayFrame);
381 }
382
383 if (handle->flags & GRALLOC_USAGE_PROTECTED)
384 align_crop_and_center(dest_w, dest_h, NULL,
385 GSC_DST_CROP_W_ALIGNMENT_RGB888);
386
387 int max_downscale = local_path ? 4 : 16;
388 const int max_upscale = 8;
389
390 return exynos5_format_is_supported_by_gscaler(format) &&
391 dst_crop_w_aligned(dest_w) &&
392 handle->stride <= max_w &&
393 handle->stride % GSC_W_ALIGNMENT == 0 &&
394 src_w <= dest_w * max_downscale &&
395 dest_w <= src_w * max_upscale &&
396 handle->vstride <= max_h &&
397 handle->vstride % GSC_H_ALIGNMENT == 0 &&
398 src_h <= dest_h * max_downscale &&
399 dest_h <= src_h * max_upscale &&
400 // per 46.2
401 (!rot90or270 || layer.sourceCrop.top % 2 == 0) &&
402 (!rot90or270 || layer.sourceCrop.left % 2 == 0);
403 // per 46.3.1.6
404 }
405
exynos5_requires_gscaler(hwc_layer_1_t & layer,int format)406 static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format)
407 {
408 return exynos5_format_requires_gscaler(format) || is_scaled(layer)
409 || is_transformed(layer) || !is_x_aligned(layer, format);
410 }
411
hdmi_get_config(struct exynos5_hwc_composer_device_1_t * dev)412 int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev)
413 {
414 struct v4l2_dv_preset preset;
415 struct v4l2_dv_enum_preset enum_preset;
416 int index = 0;
417 bool found = false;
418 int ret;
419
420 if (ioctl(dev->hdmi_layers[0].fd, VIDIOC_G_DV_PRESET, &preset) < 0) {
421 ALOGE("%s: g_dv_preset error, %d", __func__, errno);
422 return -1;
423 }
424
425 while (true) {
426 enum_preset.index = index++;
427 ret = ioctl(dev->hdmi_layers[0].fd, VIDIOC_ENUM_DV_PRESETS, &enum_preset);
428
429 if (ret < 0) {
430 if (errno == EINVAL)
431 break;
432 ALOGE("%s: enum_dv_presets error, %d", __func__, errno);
433 return -1;
434 }
435
436 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s",
437 __func__, enum_preset.index, enum_preset.preset,
438 enum_preset.width, enum_preset.height, enum_preset.name);
439
440 if (preset.preset == enum_preset.preset) {
441 dev->hdmi_w = enum_preset.width;
442 dev->hdmi_h = enum_preset.height;
443 found = true;
444 }
445 }
446
447 return found ? 0 : -1;
448 }
449
exynos5_blending_to_s3c_blending(int32_t blending)450 static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending)
451 {
452 switch (blending) {
453 case HWC_BLENDING_NONE:
454 return S3C_FB_BLENDING_NONE;
455 case HWC_BLENDING_PREMULT:
456 return S3C_FB_BLENDING_PREMULT;
457 case HWC_BLENDING_COVERAGE:
458 return S3C_FB_BLENDING_COVERAGE;
459
460 default:
461 return S3C_FB_BLENDING_MAX;
462 }
463 }
464
exynos5_blending_is_supported(int32_t blending)465 static bool exynos5_blending_is_supported(int32_t blending)
466 {
467 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX;
468 }
469
470
hdmi_enable_layer(struct exynos5_hwc_composer_device_1_t * dev,hdmi_layer_t & hl)471 static int hdmi_enable_layer(struct exynos5_hwc_composer_device_1_t *dev,
472 hdmi_layer_t &hl)
473 {
474 if (hl.enabled)
475 return 0;
476
477 struct v4l2_requestbuffers reqbuf;
478 memset(&reqbuf, 0, sizeof(reqbuf));
479 reqbuf.count = NUM_HDMI_BUFFERS;
480 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
481 reqbuf.memory = V4L2_MEMORY_DMABUF;
482 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) {
483 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno);
484 return -1;
485 }
486
487 if (reqbuf.count != NUM_HDMI_BUFFERS) {
488 ALOGE("%s: layer%d: didn't get buffer", __func__, hl.id);
489 return -1;
490 }
491
492 if (hl.id == 1) {
493 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_PIXEL_BLEND_ENABLE, 1) < 0) {
494 ALOGE("%s: layer%d: PIXEL_BLEND_ENABLE failed %d", __func__,
495 hl.id, errno);
496 return -1;
497 }
498 }
499
500 ALOGV("%s: layer%d enabled", __func__, hl.id);
501 hl.enabled = true;
502 return 0;
503 }
504
hdmi_disable_layer(struct exynos5_hwc_composer_device_1_t * dev,hdmi_layer_t & hl)505 static void hdmi_disable_layer(struct exynos5_hwc_composer_device_1_t *dev,
506 hdmi_layer_t &hl)
507 {
508 if (!hl.enabled)
509 return;
510
511 if (hl.streaming) {
512 if (exynos_v4l2_streamoff(hl.fd, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0)
513 ALOGE("%s: layer%d: streamoff failed %d", __func__, hl.id, errno);
514 hl.streaming = false;
515 }
516
517 struct v4l2_requestbuffers reqbuf;
518 memset(&reqbuf, 0, sizeof(reqbuf));
519 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
520 reqbuf.memory = V4L2_MEMORY_DMABUF;
521 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0)
522 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno);
523
524 memset(&hl.cfg, 0, sizeof(hl.cfg));
525 hl.current_buf = 0;
526 hl.queued_buf = 0;
527 hl.enabled = false;
528
529 ALOGV("%s: layer%d disabled", __func__, hl.id);
530 }
531
hdmi_hide_layer(struct exynos5_hwc_composer_device_1_t * dev,hdmi_layer_t & hl)532 static void hdmi_hide_layer(struct exynos5_hwc_composer_device_1_t *dev,
533 hdmi_layer_t &hl)
534 {
535 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_LAYER_PRIO, 0) < 0)
536 ALOGE("%s: layer%d: LAYER_PRIO failed %d", __func__,
537 hl.id, errno);
538 }
539
hdmi_show_layer(struct exynos5_hwc_composer_device_1_t * dev,hdmi_layer_t & hl)540 static void hdmi_show_layer(struct exynos5_hwc_composer_device_1_t *dev,
541 hdmi_layer_t &hl)
542 {
543 int prio = hl.id ? 3 : 2;
544
545 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_LAYER_PRIO, prio) < 0)
546 ALOGE("%s: layer%d: LAYER_PRIO failed %d", __func__,
547 hl.id, errno);
548 }
549
hdmi_enable(struct exynos5_hwc_composer_device_1_t * dev)550 static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev)
551 {
552 if (dev->hdmi_enabled)
553 return 0;
554
555 if (dev->hdmi_blanked)
556 return 0;
557
558 struct v4l2_subdev_format sd_fmt;
559 memset(&sd_fmt, 0, sizeof(sd_fmt));
560 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SINK;
561 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
562 sd_fmt.format.width = dev->hdmi_w;
563 sd_fmt.format.height = dev->hdmi_h;
564 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE;
565 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) {
566 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad);
567 return -1;
568 }
569
570 struct v4l2_subdev_crop sd_crop;
571 memset(&sd_crop, 0, sizeof(sd_crop));
572 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SINK;
573 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE;
574 sd_crop.rect.width = dev->hdmi_w;
575 sd_crop.rect.height = dev->hdmi_h;
576 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) {
577 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad);
578 return -1;
579 }
580
581 memset(&sd_fmt, 0, sizeof(sd_fmt));
582 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SOURCE;
583 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
584 sd_fmt.format.width = dev->hdmi_w;
585 sd_fmt.format.height = dev->hdmi_h;
586 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE;
587 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) {
588 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad);
589 return -1;
590 }
591
592 memset(&sd_crop, 0, sizeof(sd_crop));
593 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE;
594 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE;
595 sd_crop.rect.width = dev->hdmi_w;
596 sd_crop.rect.height = dev->hdmi_h;
597 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) {
598 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad);
599 return -1;
600 }
601
602 char value[PROPERTY_VALUE_MAX];
603 property_get("persist.hdmi.hdcp_enabled", value, "1");
604 int hdcp_enabled = atoi(value);
605
606 if (exynos_v4l2_s_ctrl(dev->hdmi_layers[1].fd, V4L2_CID_TV_HDCP_ENABLE,
607 hdcp_enabled) < 0)
608 ALOGE("%s: s_ctrl(CID_TV_HDCP_ENABLE) failed %d", __func__, errno);
609
610 /* "3" is RGB709_16_235 */
611 property_get("persist.hdmi.color_range", value, "3");
612 int color_range = atoi(value);
613
614 if (exynos_v4l2_s_ctrl(dev->hdmi_layers[1].fd, V4L2_CID_TV_SET_COLOR_RANGE,
615 color_range) < 0)
616 ALOGE("%s: s_ctrl(CID_TV_COLOR_RANGE) failed %d", __func__, errno);
617
618 hdmi_enable_layer(dev, dev->hdmi_layers[1]);
619
620 dev->hdmi_enabled = true;
621 return 0;
622 }
623
hdmi_disable(struct exynos5_hwc_composer_device_1_t * dev)624 static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev)
625 {
626 if (!dev->hdmi_enabled)
627 return;
628
629 hdmi_disable_layer(dev, dev->hdmi_layers[0]);
630 hdmi_disable_layer(dev, dev->hdmi_layers[1]);
631
632 exynos5_cleanup_gsc_m2m(dev, HDMI_GSC_IDX);
633 dev->hdmi_enabled = false;
634 }
635
hdmi_output(struct exynos5_hwc_composer_device_1_t * dev,hdmi_layer_t & hl,hwc_layer_1_t & layer,private_handle_t * h,int acquireFenceFd,int * releaseFenceFd)636 static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev,
637 hdmi_layer_t &hl,
638 hwc_layer_1_t &layer,
639 private_handle_t *h,
640 int acquireFenceFd,
641 int *releaseFenceFd)
642 {
643 int ret = 0;
644
645 exynos_gsc_img cfg;
646 memset(&cfg, 0, sizeof(cfg));
647 cfg.x = layer.displayFrame.left;
648 cfg.y = layer.displayFrame.top;
649 cfg.w = WIDTH(layer.displayFrame);
650 cfg.h = HEIGHT(layer.displayFrame);
651
652 if (gsc_src_cfg_changed(hl.cfg, cfg)) {
653 hdmi_disable_layer(dev, hl);
654
655 struct v4l2_format fmt;
656 memset(&fmt, 0, sizeof(fmt));
657 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
658 fmt.fmt.pix_mp.width = h->stride;
659 fmt.fmt.pix_mp.height = cfg.h;
660 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32;
661 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY;
662 fmt.fmt.pix_mp.num_planes = 1;
663 ret = exynos_v4l2_s_fmt(hl.fd, &fmt);
664 if (ret < 0) {
665 ALOGE("%s: layer%d: s_fmt failed %d", __func__, hl.id, errno);
666 goto err;
667 }
668
669 struct v4l2_subdev_crop sd_crop;
670 memset(&sd_crop, 0, sizeof(sd_crop));
671 if (hl.id == 0)
672 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE;
673 else
674 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE;
675 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE;
676 sd_crop.rect.left = cfg.x;
677 sd_crop.rect.top = cfg.y;
678 sd_crop.rect.width = cfg.w;
679 sd_crop.rect.height = cfg.h;
680 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) {
681 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad);
682 goto err;
683 }
684
685 hdmi_enable_layer(dev, hl);
686
687 ALOGV("HDMI layer%d configuration:", hl.id);
688 dump_gsc_img(cfg);
689 hl.cfg = cfg;
690 }
691
692 struct v4l2_buffer buffer;
693 struct v4l2_plane planes[1];
694
695 if (hl.queued_buf == NUM_HDMI_BUFFERS) {
696 memset(&buffer, 0, sizeof(buffer));
697 memset(planes, 0, sizeof(planes));
698 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
699 buffer.memory = V4L2_MEMORY_DMABUF;
700 buffer.length = 1;
701 buffer.m.planes = planes;
702 ret = exynos_v4l2_dqbuf(hl.fd, &buffer);
703 if (ret < 0) {
704 ALOGE("%s: layer%d: dqbuf failed %d", __func__, hl.id, errno);
705 goto err;
706 }
707 hl.queued_buf--;
708 }
709
710 memset(&buffer, 0, sizeof(buffer));
711 memset(planes, 0, sizeof(planes));
712 buffer.index = hl.current_buf;
713 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
714 buffer.memory = V4L2_MEMORY_DMABUF;
715 buffer.flags = V4L2_BUF_FLAG_USE_SYNC;
716 buffer.reserved = acquireFenceFd;
717 buffer.length = 1;
718 buffer.m.planes = planes;
719 buffer.m.planes[0].m.fd = h->fd;
720 if (exynos_v4l2_qbuf(hl.fd, &buffer) < 0) {
721 ALOGE("%s: layer%d: qbuf failed %d", __func__, hl.id, errno);
722 ret = -1;
723 goto err;
724 }
725
726 if (releaseFenceFd)
727 *releaseFenceFd = buffer.reserved;
728 else
729 close(buffer.reserved);
730
731 hl.queued_buf++;
732 hl.current_buf = (hl.current_buf + 1) % NUM_HDMI_BUFFERS;
733
734 if (!hl.streaming) {
735 if (exynos_v4l2_streamon(hl.fd, buffer.type) < 0) {
736 ALOGE("%s: layer%d: streamon failed %d", __func__, hl.id, errno);
737 ret = -1;
738 goto err;
739 }
740 hl.streaming = true;
741 }
742
743 err:
744 if (acquireFenceFd >= 0)
745 close(acquireFenceFd);
746
747 return ret;
748 }
749
exynos5_is_offscreen(hwc_layer_1_t & layer,struct exynos5_hwc_composer_device_1_t * pdev)750 bool exynos5_is_offscreen(hwc_layer_1_t &layer,
751 struct exynos5_hwc_composer_device_1_t *pdev)
752 {
753 return layer.sourceCrop.left > pdev->xres ||
754 layer.sourceCrop.right < 0 ||
755 layer.sourceCrop.top > pdev->yres ||
756 layer.sourceCrop.bottom < 0;
757 }
758
exynos5_visible_width(hwc_layer_1_t & layer,int format,struct exynos5_hwc_composer_device_1_t * pdev)759 size_t exynos5_visible_width(hwc_layer_1_t &layer, int format,
760 struct exynos5_hwc_composer_device_1_t *pdev)
761 {
762 int bpp;
763 if (exynos5_requires_gscaler(layer, format))
764 bpp = 32;
765 else
766 bpp = exynos5_format_to_bpp(format);
767 int left = max(layer.displayFrame.left, 0);
768 int right = min(layer.displayFrame.right, pdev->xres);
769
770 return (right - left) * bpp / 8;
771 }
772
exynos5_supports_overlay(hwc_layer_1_t & layer,size_t i,struct exynos5_hwc_composer_device_1_t * pdev)773 bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i,
774 struct exynos5_hwc_composer_device_1_t *pdev)
775 {
776 if (layer.flags & HWC_SKIP_LAYER) {
777 ALOGV("\tlayer %u: skipping", i);
778 return false;
779 }
780
781 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle);
782
783 if (!handle) {
784 ALOGV("\tlayer %u: handle is NULL", i);
785 return false;
786 }
787
788 if (exynos5_visible_width(layer, handle->format, pdev) < BURSTLEN_BYTES) {
789 ALOGV("\tlayer %u: visible area is too narrow", i);
790 return false;
791 }
792 if (exynos5_requires_gscaler(layer, handle->format)) {
793 if (!exynos5_supports_gscaler(layer, handle->format, false)) {
794 ALOGV("\tlayer %u: gscaler required but not supported", i);
795 return false;
796 }
797 } else {
798 if (!exynos5_format_is_supported(handle->format)) {
799 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format);
800 return false;
801 }
802 }
803 if (!exynos5_blending_is_supported(layer.blending)) {
804 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending);
805 return false;
806 }
807 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) {
808 ALOGW("\tlayer %u: off-screen", i);
809 return false;
810 }
811
812 return true;
813 }
814
intersect(const hwc_rect & r1,const hwc_rect & r2)815 inline bool intersect(const hwc_rect &r1, const hwc_rect &r2)
816 {
817 return !(r1.left > r2.right ||
818 r1.right < r2.left ||
819 r1.top > r2.bottom ||
820 r1.bottom < r2.top);
821 }
822
intersection(const hwc_rect & r1,const hwc_rect & r2)823 inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2)
824 {
825 hwc_rect i;
826 i.top = max(r1.top, r2.top);
827 i.bottom = min(r1.bottom, r2.bottom);
828 i.left = max(r1.left, r2.left);
829 i.right = min(r1.right, r2.right);
830 return i;
831 }
832
exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t * pdev,hwc_display_contents_1_t * contents)833 static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev,
834 hwc_display_contents_1_t* contents)
835 {
836 ALOGV("preparing %u layers for FIMD", contents->numHwLayers);
837
838 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map));
839
840 bool force_fb = pdev->force_gpu;
841 for (size_t i = 0; i < NUM_HW_WINDOWS; i++)
842 pdev->bufs.overlay_map[i] = -1;
843
844 bool fb_needed = false;
845 size_t first_fb = 0, last_fb = 0;
846
847 // find unsupported overlays
848 for (size_t i = 0; i < contents->numHwLayers; i++) {
849 hwc_layer_1_t &layer = contents->hwLayers[i];
850
851 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) {
852 ALOGV("\tlayer %u: framebuffer target", i);
853 continue;
854 }
855
856 if (layer.compositionType == HWC_BACKGROUND && !force_fb) {
857 ALOGV("\tlayer %u: background supported", i);
858 dump_layer(&contents->hwLayers[i]);
859 continue;
860 }
861
862 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) &&
863 !force_fb) {
864 ALOGV("\tlayer %u: overlay supported", i);
865 layer.compositionType = HWC_OVERLAY;
866 dump_layer(&contents->hwLayers[i]);
867 continue;
868 }
869
870 if (!fb_needed) {
871 first_fb = i;
872 fb_needed = true;
873 }
874 last_fb = i;
875 layer.compositionType = HWC_FRAMEBUFFER;
876
877 dump_layer(&contents->hwLayers[i]);
878 }
879
880 // can't composite overlays sandwiched between framebuffers
881 if (fb_needed)
882 for (size_t i = first_fb; i < last_fb; i++)
883 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER;
884
885 // Incrementally try to add our supported layers to hardware windows.
886 // If adding a layer would violate a hardware constraint, force it
887 // into the framebuffer and try again. (Revisiting the entire list is
888 // necessary because adding a layer to the framebuffer can cause other
889 // windows to retroactively violate constraints.)
890 bool changed;
891 bool gsc_used;
892 do {
893 android::Vector<hwc_rect> rects;
894 android::Vector<hwc_rect> overlaps;
895 size_t pixels_left, windows_left;
896
897 gsc_used = false;
898
899 if (fb_needed) {
900 hwc_rect_t fb_rect;
901 fb_rect.top = fb_rect.left = 0;
902 fb_rect.right = pdev->xres - 1;
903 fb_rect.bottom = pdev->yres - 1;
904 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres;
905 windows_left = NUM_HW_WINDOWS - 1;
906 rects.push_back(fb_rect);
907 }
908 else {
909 pixels_left = MAX_PIXELS;
910 windows_left = NUM_HW_WINDOWS;
911 }
912
913 changed = false;
914
915 for (size_t i = 0; i < contents->numHwLayers; i++) {
916 hwc_layer_1_t &layer = contents->hwLayers[i];
917 if ((layer.flags & HWC_SKIP_LAYER) ||
918 layer.compositionType == HWC_FRAMEBUFFER_TARGET)
919 continue;
920
921 private_handle_t *handle = private_handle_t::dynamicCast(
922 layer.handle);
923
924 // we've already accounted for the framebuffer above
925 if (layer.compositionType == HWC_FRAMEBUFFER)
926 continue;
927
928 // only layer 0 can be HWC_BACKGROUND, so we can
929 // unconditionally allow it without extra checks
930 if (layer.compositionType == HWC_BACKGROUND) {
931 windows_left--;
932 continue;
933 }
934
935 size_t pixels_needed = WIDTH(layer.displayFrame) *
936 HEIGHT(layer.displayFrame);
937 bool can_compose = windows_left && pixels_needed <= pixels_left;
938 bool gsc_required = exynos5_requires_gscaler(layer, handle->format);
939 if (gsc_required)
940 can_compose = can_compose && !gsc_used;
941
942 // hwc_rect_t right and bottom values are normally exclusive;
943 // the intersection logic is simpler if we make them inclusive
944 hwc_rect_t visible_rect = layer.displayFrame;
945 visible_rect.right--; visible_rect.bottom--;
946
947 // no more than 2 layers can overlap on a given pixel
948 for (size_t j = 0; can_compose && j < overlaps.size(); j++) {
949 if (intersect(visible_rect, overlaps.itemAt(j)))
950 can_compose = false;
951 }
952
953 if (!can_compose) {
954 layer.compositionType = HWC_FRAMEBUFFER;
955 if (!fb_needed) {
956 first_fb = last_fb = i;
957 fb_needed = true;
958 }
959 else {
960 first_fb = min(i, first_fb);
961 last_fb = max(i, last_fb);
962 }
963 changed = true;
964 break;
965 }
966
967 for (size_t j = 0; j < rects.size(); j++) {
968 const hwc_rect_t &other_rect = rects.itemAt(j);
969 if (intersect(visible_rect, other_rect))
970 overlaps.push_back(intersection(visible_rect, other_rect));
971 }
972 rects.push_back(visible_rect);
973 pixels_left -= pixels_needed;
974 windows_left--;
975 if (gsc_required)
976 gsc_used = true;
977 }
978
979 if (changed)
980 for (size_t i = first_fb; i < last_fb; i++)
981 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER;
982 } while(changed);
983
984 unsigned int nextWindow = 0;
985
986 for (size_t i = 0; i < contents->numHwLayers; i++) {
987 hwc_layer_1_t &layer = contents->hwLayers[i];
988
989 if (fb_needed && i == first_fb) {
990 ALOGV("assigning framebuffer to window %u\n",
991 nextWindow);
992 nextWindow++;
993 continue;
994 }
995
996 if (layer.compositionType != HWC_FRAMEBUFFER &&
997 layer.compositionType != HWC_FRAMEBUFFER_TARGET) {
998 ALOGV("assigning layer %u to window %u", i, nextWindow);
999 pdev->bufs.overlay_map[nextWindow] = i;
1000 if (layer.compositionType == HWC_OVERLAY) {
1001 private_handle_t *handle =
1002 private_handle_t::dynamicCast(layer.handle);
1003 if (exynos5_requires_gscaler(layer, handle->format)) {
1004 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[FIMD_GSC_IDX]);
1005 pdev->bufs.gsc_map[nextWindow].mode =
1006 exynos5_gsc_map_t::GSC_M2M;
1007 pdev->bufs.gsc_map[nextWindow].idx = FIMD_GSC_IDX;
1008 }
1009 }
1010 nextWindow++;
1011 }
1012 }
1013
1014 if (!gsc_used)
1015 exynos5_cleanup_gsc_m2m(pdev, FIMD_GSC_IDX);
1016
1017 if (fb_needed)
1018 pdev->bufs.fb_window = first_fb;
1019 else
1020 pdev->bufs.fb_window = NO_FB_NEEDED;
1021
1022 return 0;
1023 }
1024
exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t * pdev,hwc_display_contents_1_t * contents)1025 static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev,
1026 hwc_display_contents_1_t* contents)
1027 {
1028 ALOGV("preparing %u layers for HDMI", contents->numHwLayers);
1029 hwc_layer_1_t *video_layer = NULL;
1030
1031 pdev->hdmi_fb_needed = false;
1032
1033 for (size_t i = 0; i < contents->numHwLayers; i++) {
1034 hwc_layer_1_t &layer = contents->hwLayers[i];
1035
1036 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) {
1037 ALOGV("\tlayer %u: framebuffer target", i);
1038 continue;
1039 }
1040
1041 if (layer.compositionType == HWC_BACKGROUND) {
1042 ALOGV("\tlayer %u: background layer", i);
1043 dump_layer(&layer);
1044 continue;
1045 }
1046
1047 if (layer.handle) {
1048 private_handle_t *h = private_handle_t::dynamicCast(layer.handle);
1049 if (h->flags & GRALLOC_USAGE_PROTECTED) {
1050 if (!video_layer) {
1051 video_layer = &layer;
1052 layer.compositionType = HWC_OVERLAY;
1053 ALOGV("\tlayer %u: video layer", i);
1054 dump_layer(&layer);
1055 continue;
1056 }
1057 }
1058 }
1059
1060 pdev->hdmi_fb_needed = true;
1061 layer.compositionType = HWC_FRAMEBUFFER;
1062 dump_layer(&layer);
1063 }
1064
1065 return 0;
1066 }
1067
exynos5_prepare(hwc_composer_device_1_t * dev,size_t numDisplays,hwc_display_contents_1_t ** displays)1068 static int exynos5_prepare(hwc_composer_device_1_t *dev,
1069 size_t numDisplays, hwc_display_contents_1_t** displays)
1070 {
1071 if (!numDisplays || !displays)
1072 return 0;
1073
1074 exynos5_hwc_composer_device_1_t *pdev =
1075 (exynos5_hwc_composer_device_1_t *)dev;
1076 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY];
1077 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL];
1078
1079 if (pdev->hdmi_hpd) {
1080 hdmi_enable(pdev);
1081 } else {
1082 hdmi_disable(pdev);
1083 }
1084
1085 if (fimd_contents) {
1086 int err = exynos5_prepare_fimd(pdev, fimd_contents);
1087 if (err)
1088 return err;
1089 }
1090
1091 if (hdmi_contents) {
1092 int err = exynos5_prepare_hdmi(pdev, hdmi_contents);
1093 if (err)
1094 return err;
1095 }
1096
1097 return 0;
1098 }
1099
exynos5_config_gsc_m2m(hwc_layer_1_t & layer,alloc_device_t * alloc_device,exynos5_gsc_data_t * gsc_data,int gsc_idx,int dst_format,hwc_rect_t * sourceCrop)1100 static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer,
1101 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data,
1102 int gsc_idx, int dst_format, hwc_rect_t *sourceCrop)
1103 {
1104 ALOGV("configuring gscaler %u for memory-to-memory", AVAILABLE_GSC_UNITS[gsc_idx]);
1105
1106 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle);
1107 buffer_handle_t dst_buf;
1108 private_handle_t *dst_handle;
1109 int ret = 0;
1110
1111 exynos_gsc_img src_cfg, dst_cfg;
1112 memset(&src_cfg, 0, sizeof(src_cfg));
1113 memset(&dst_cfg, 0, sizeof(dst_cfg));
1114
1115 hwc_rect_t sourceCropTemp;
1116 if (!sourceCrop)
1117 sourceCrop = &sourceCropTemp;
1118
1119 src_cfg.x = layer.sourceCrop.left;
1120 src_cfg.y = layer.sourceCrop.top;
1121 src_cfg.w = WIDTH(layer.sourceCrop);
1122 src_cfg.fw = src_handle->stride;
1123 src_cfg.h = HEIGHT(layer.sourceCrop);
1124 src_cfg.fh = src_handle->vstride;
1125 src_cfg.yaddr = src_handle->fd;
1126 if (exynos5_format_is_ycrcb(src_handle->format)) {
1127 src_cfg.uaddr = src_handle->fd2;
1128 src_cfg.vaddr = src_handle->fd1;
1129 } else {
1130 src_cfg.uaddr = src_handle->fd1;
1131 src_cfg.vaddr = src_handle->fd2;
1132 }
1133 src_cfg.format = src_handle->format;
1134 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED);
1135 src_cfg.acquireFenceFd = layer.acquireFenceFd;
1136 layer.acquireFenceFd = -1;
1137
1138 dst_cfg.x = 0;
1139 dst_cfg.y = 0;
1140 dst_cfg.w = WIDTH(layer.displayFrame);
1141 dst_cfg.h = HEIGHT(layer.displayFrame);
1142 dst_cfg.rot = layer.transform;
1143 dst_cfg.drmMode = src_cfg.drmMode;
1144 dst_cfg.format = dst_format;
1145 dst_cfg.narrowRgb = !exynos5_format_is_rgb(src_handle->format);
1146 if (dst_cfg.drmMode)
1147 align_crop_and_center(dst_cfg.w, dst_cfg.h, sourceCrop,
1148 GSC_DST_CROP_W_ALIGNMENT_RGB888);
1149
1150 ALOGV("source configuration:");
1151 dump_gsc_img(src_cfg);
1152
1153 bool reconfigure = gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) ||
1154 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg);
1155 if (reconfigure) {
1156 int dst_stride;
1157 int usage = GRALLOC_USAGE_SW_READ_NEVER |
1158 GRALLOC_USAGE_SW_WRITE_NEVER |
1159 GRALLOC_USAGE_HW_COMPOSER;
1160
1161 if (src_handle->flags & GRALLOC_USAGE_PROTECTED)
1162 usage |= GRALLOC_USAGE_PROTECTED;
1163
1164 int w = ALIGN(dst_cfg.w, GSC_DST_W_ALIGNMENT_RGB888);
1165 int h = ALIGN(dst_cfg.h, GSC_DST_H_ALIGNMENT_RGB888);
1166
1167 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) {
1168 if (gsc_data->dst_buf[i]) {
1169 alloc_device->free(alloc_device, gsc_data->dst_buf[i]);
1170 gsc_data->dst_buf[i] = NULL;
1171 }
1172
1173 if (gsc_data->dst_buf_fence[i] >= 0) {
1174 close(gsc_data->dst_buf_fence[i]);
1175 gsc_data->dst_buf_fence[i] = -1;
1176 }
1177
1178 int ret = alloc_device->alloc(alloc_device, w, h,
1179 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i],
1180 &dst_stride);
1181 if (ret < 0) {
1182 ALOGE("failed to allocate destination buffer: %s",
1183 strerror(-ret));
1184 goto err_alloc;
1185 }
1186 }
1187
1188 gsc_data->current_buf = 0;
1189 }
1190
1191 dst_buf = gsc_data->dst_buf[gsc_data->current_buf];
1192 dst_handle = private_handle_t::dynamicCast(dst_buf);
1193
1194 dst_cfg.fw = dst_handle->stride;
1195 dst_cfg.fh = dst_handle->vstride;
1196 dst_cfg.yaddr = dst_handle->fd;
1197 dst_cfg.acquireFenceFd = gsc_data->dst_buf_fence[gsc_data->current_buf];
1198 gsc_data->dst_buf_fence[gsc_data->current_buf] = -1;
1199
1200 ALOGV("destination configuration:");
1201 dump_gsc_img(dst_cfg);
1202
1203 if ((int)dst_cfg.w != WIDTH(layer.displayFrame))
1204 ALOGV("padding %u x %u output to %u x %u and cropping to {%u,%u,%u,%u}",
1205 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame),
1206 dst_cfg.w, dst_cfg.h, sourceCrop->left, sourceCrop->top,
1207 sourceCrop->right, sourceCrop->bottom);
1208
1209 if (gsc_data->gsc) {
1210 ALOGV("reusing open gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]);
1211 } else {
1212 ALOGV("opening gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]);
1213 gsc_data->gsc = exynos_gsc_create_exclusive(
1214 AVAILABLE_GSC_UNITS[gsc_idx], GSC_M2M_MODE, GSC_DUMMY, true);
1215 if (!gsc_data->gsc) {
1216 ALOGE("failed to create gscaler handle");
1217 ret = -1;
1218 goto err_alloc;
1219 }
1220 }
1221
1222 if (reconfigure) {
1223 ret = exynos_gsc_stop_exclusive(gsc_data->gsc);
1224 if (ret < 0) {
1225 ALOGE("failed to stop gscaler %u", gsc_idx);
1226 goto err_gsc_config;
1227 }
1228
1229 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg);
1230 if (ret < 0) {
1231 ALOGE("failed to configure gscaler %u", gsc_idx);
1232 goto err_gsc_config;
1233 }
1234 }
1235
1236 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg);
1237 if (ret < 0) {
1238 ALOGE("failed to run gscaler %u", gsc_idx);
1239 goto err_gsc_config;
1240 }
1241
1242 gsc_data->src_cfg = src_cfg;
1243 gsc_data->dst_cfg = dst_cfg;
1244
1245 layer.releaseFenceFd = src_cfg.releaseFenceFd;
1246
1247 return 0;
1248
1249 err_gsc_config:
1250 exynos_gsc_destroy(gsc_data->gsc);
1251 gsc_data->gsc = NULL;
1252 err_alloc:
1253 if (src_cfg.acquireFenceFd >= 0)
1254 close(src_cfg.acquireFenceFd);
1255 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) {
1256 if (gsc_data->dst_buf[i]) {
1257 alloc_device->free(alloc_device, gsc_data->dst_buf[i]);
1258 gsc_data->dst_buf[i] = NULL;
1259 }
1260 if (gsc_data->dst_buf_fence[i] >= 0) {
1261 close(gsc_data->dst_buf_fence[i]);
1262 gsc_data->dst_buf_fence[i] = -1;
1263 }
1264 }
1265 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg));
1266 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg));
1267 return ret;
1268 }
1269
1270
exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t * pdev,size_t gsc_idx)1271 static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev,
1272 size_t gsc_idx)
1273 {
1274 exynos5_gsc_data_t &gsc_data = pdev->gsc[gsc_idx];
1275 if (!gsc_data.gsc)
1276 return;
1277
1278 ALOGV("closing gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]);
1279
1280 exynos_gsc_stop_exclusive(gsc_data.gsc);
1281 exynos_gsc_destroy(gsc_data.gsc);
1282 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) {
1283 if (gsc_data.dst_buf[i])
1284 pdev->alloc_device->free(pdev->alloc_device, gsc_data.dst_buf[i]);
1285 if (gsc_data.dst_buf_fence[i] >= 0)
1286 close(gsc_data.dst_buf_fence[i]);
1287 }
1288
1289 memset(&gsc_data, 0, sizeof(gsc_data));
1290 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++)
1291 gsc_data.dst_buf_fence[i] = -1;
1292 }
1293
exynos5_config_handle(private_handle_t * handle,hwc_rect_t & sourceCrop,hwc_rect_t & displayFrame,int32_t blending,int fence_fd,s3c_fb_win_config & cfg,exynos5_hwc_composer_device_1_t * pdev)1294 static void exynos5_config_handle(private_handle_t *handle,
1295 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame,
1296 int32_t blending, int fence_fd, s3c_fb_win_config &cfg,
1297 exynos5_hwc_composer_device_1_t *pdev)
1298 {
1299 uint32_t x, y;
1300 uint32_t w = WIDTH(displayFrame);
1301 uint32_t h = HEIGHT(displayFrame);
1302 uint8_t bpp = exynos5_format_to_bpp(handle->format);
1303 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8;
1304
1305 if (displayFrame.left < 0) {
1306 unsigned int crop = -displayFrame.left;
1307 ALOGV("layer off left side of screen; cropping %u pixels from left edge",
1308 crop);
1309 x = 0;
1310 w -= crop;
1311 offset += crop * bpp / 8;
1312 } else {
1313 x = displayFrame.left;
1314 }
1315
1316 if (displayFrame.right > pdev->xres) {
1317 unsigned int crop = displayFrame.right - pdev->xres;
1318 ALOGV("layer off right side of screen; cropping %u pixels from right edge",
1319 crop);
1320 w -= crop;
1321 }
1322
1323 if (displayFrame.top < 0) {
1324 unsigned int crop = -displayFrame.top;
1325 ALOGV("layer off top side of screen; cropping %u pixels from top edge",
1326 crop);
1327 y = 0;
1328 h -= crop;
1329 offset += handle->stride * crop * bpp / 8;
1330 } else {
1331 y = displayFrame.top;
1332 }
1333
1334 if (displayFrame.bottom > pdev->yres) {
1335 int crop = displayFrame.bottom - pdev->yres;
1336 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge",
1337 crop);
1338 h -= crop;
1339 }
1340
1341 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER;
1342 cfg.fd = handle->fd;
1343 cfg.x = x;
1344 cfg.y = y;
1345 cfg.w = w;
1346 cfg.h = h;
1347 cfg.format = exynos5_format_to_s3c_format(handle->format);
1348 cfg.offset = offset;
1349 cfg.stride = handle->stride * bpp / 8;
1350 cfg.blending = exynos5_blending_to_s3c_blending(blending);
1351 cfg.fence_fd = fence_fd;
1352 }
1353
exynos5_config_overlay(hwc_layer_1_t * layer,s3c_fb_win_config & cfg,exynos5_hwc_composer_device_1_t * pdev)1354 static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg,
1355 exynos5_hwc_composer_device_1_t *pdev)
1356 {
1357 if (layer->compositionType == HWC_BACKGROUND) {
1358 hwc_color_t color = layer->backgroundColor;
1359 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR;
1360 cfg.color = (color.r << 16) | (color.g << 8) | color.b;
1361 cfg.x = 0;
1362 cfg.y = 0;
1363 cfg.w = pdev->xres;
1364 cfg.h = pdev->yres;
1365 return;
1366 }
1367
1368 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle);
1369 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame,
1370 layer->blending, layer->acquireFenceFd, cfg, pdev);
1371 }
1372
exynos5_post_fimd(exynos5_hwc_composer_device_1_t * pdev,hwc_display_contents_1_t * contents)1373 static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev,
1374 hwc_display_contents_1_t* contents)
1375 {
1376 exynos5_hwc_post_data_t *pdata = &pdev->bufs;
1377 struct s3c_fb_win_config_data win_data;
1378 struct s3c_fb_win_config *config = win_data.config;
1379
1380 memset(config, 0, sizeof(win_data.config));
1381 for (size_t i = 0; i < NUM_HW_WINDOWS; i++)
1382 config[i].fence_fd = -1;
1383
1384 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) {
1385 int layer_idx = pdata->overlay_map[i];
1386 if (layer_idx != -1) {
1387 hwc_layer_1_t &layer = contents->hwLayers[layer_idx];
1388 private_handle_t *handle =
1389 private_handle_t::dynamicCast(layer.handle);
1390
1391 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) {
1392 int gsc_idx = pdata->gsc_map[i].idx;
1393 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx];
1394
1395 // RGBX8888 surfaces are already in the right color order from the GPU,
1396 // RGB565 and YUV surfaces need the Gscaler to swap R & B
1397 int dst_format = HAL_PIXEL_FORMAT_BGRA_8888;
1398 if (exynos5_format_is_rgb(handle->format) &&
1399 handle->format != HAL_PIXEL_FORMAT_RGB_565)
1400 dst_format = HAL_PIXEL_FORMAT_RGBX_8888;
1401
1402 hwc_rect_t sourceCrop = { 0, 0,
1403 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) };
1404 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc,
1405 gsc_idx, dst_format, &sourceCrop);
1406 if (err < 0) {
1407 ALOGE("failed to configure gscaler %u for layer %u",
1408 gsc_idx, i);
1409 pdata->gsc_map[i].mode = exynos5_gsc_map_t::GSC_NONE;
1410 continue;
1411 }
1412
1413 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf];
1414 private_handle_t *dst_handle =
1415 private_handle_t::dynamicCast(dst_buf);
1416 int fence = gsc.dst_cfg.releaseFenceFd;
1417 exynos5_config_handle(dst_handle, sourceCrop,
1418 layer.displayFrame, layer.blending, fence, config[i],
1419 pdev);
1420 } else {
1421 exynos5_config_overlay(&layer, config[i], pdev);
1422 }
1423 }
1424 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) {
1425 ALOGV("blending not supported on window 0; forcing BLENDING_NONE");
1426 config[i].blending = S3C_FB_BLENDING_NONE;
1427 }
1428
1429 ALOGV("window %u configuration:", i);
1430 dump_config(config[i]);
1431 }
1432
1433 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data);
1434 for (size_t i = 0; i < NUM_HW_WINDOWS; i++)
1435 if (config[i].fence_fd != -1)
1436 close(config[i].fence_fd);
1437 if (ret < 0) {
1438 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno));
1439 return ret;
1440 }
1441
1442 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config));
1443 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map));
1444 pdev->last_fb_window = pdata->fb_window;
1445 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) {
1446 int layer_idx = pdata->overlay_map[i];
1447 if (layer_idx != -1) {
1448 hwc_layer_1_t &layer = contents->hwLayers[layer_idx];
1449 pdev->last_handles[i] = layer.handle;
1450 }
1451 }
1452
1453 return win_data.fence;
1454 }
1455
exynos5_clear_fimd(exynos5_hwc_composer_device_1_t * pdev)1456 static int exynos5_clear_fimd(exynos5_hwc_composer_device_1_t *pdev)
1457 {
1458 struct s3c_fb_win_config_data win_data;
1459 memset(&win_data, 0, sizeof(win_data));
1460
1461 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data);
1462 LOG_ALWAYS_FATAL_IF(ret < 0,
1463 "ioctl S3CFB_WIN_CONFIG failed to clear screen: %s",
1464 strerror(errno));
1465 // the causes of an empty config failing are all unrecoverable
1466
1467 return win_data.fence;
1468 }
1469
exynos5_set_fimd(exynos5_hwc_composer_device_1_t * pdev,hwc_display_contents_1_t * contents)1470 static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev,
1471 hwc_display_contents_1_t* contents)
1472 {
1473 if (!contents->dpy || !contents->sur)
1474 return 0;
1475
1476 hwc_layer_1_t *fb_layer = NULL;
1477 int err = 0;
1478
1479 if (pdev->bufs.fb_window != NO_FB_NEEDED) {
1480 for (size_t i = 0; i < contents->numHwLayers; i++) {
1481 if (contents->hwLayers[i].compositionType ==
1482 HWC_FRAMEBUFFER_TARGET) {
1483 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i;
1484 fb_layer = &contents->hwLayers[i];
1485 break;
1486 }
1487 }
1488
1489 if (CC_UNLIKELY(!fb_layer)) {
1490 ALOGE("framebuffer target expected, but not provided");
1491 err = -EINVAL;
1492 } else {
1493 ALOGV("framebuffer target buffer:");
1494 dump_layer(fb_layer);
1495 }
1496 }
1497
1498 int fence;
1499 if (!err) {
1500 fence = exynos5_post_fimd(pdev, contents);
1501 if (fence < 0)
1502 err = fence;
1503 }
1504
1505 if (err)
1506 fence = exynos5_clear_fimd(pdev);
1507
1508 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) {
1509 if (pdev->bufs.overlay_map[i] != -1) {
1510 hwc_layer_1_t &layer =
1511 contents->hwLayers[pdev->bufs.overlay_map[i]];
1512 int dup_fd = dup(fence);
1513 if (dup_fd < 0)
1514 ALOGW("release fence dup failed: %s", strerror(errno));
1515 if (pdev->bufs.gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) {
1516 int gsc_idx = pdev->bufs.gsc_map[i].idx;
1517 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx];
1518 gsc.dst_buf_fence[gsc.current_buf] = dup_fd;
1519 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS;
1520 } else {
1521 layer.releaseFenceFd = dup_fd;
1522 }
1523 }
1524 }
1525 close(fence);
1526
1527 return err;
1528 }
1529
exynos5_set_hdmi(exynos5_hwc_composer_device_1_t * pdev,hwc_display_contents_1_t * contents)1530 static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev,
1531 hwc_display_contents_1_t* contents)
1532 {
1533 hwc_layer_1_t *video_layer = NULL;
1534
1535 if (!pdev->hdmi_enabled) {
1536 for (size_t i = 0; i < contents->numHwLayers; i++) {
1537 hwc_layer_1_t &layer = contents->hwLayers[i];
1538 if (layer.acquireFenceFd != -1) {
1539 close(layer.acquireFenceFd);
1540 layer.acquireFenceFd = -1;
1541 }
1542 }
1543 return 0;
1544 }
1545
1546 for (size_t i = 0; i < contents->numHwLayers; i++) {
1547 hwc_layer_1_t &layer = contents->hwLayers[i];
1548
1549 if (layer.flags & HWC_SKIP_LAYER) {
1550 ALOGV("HDMI skipping layer %d", i);
1551 continue;
1552 }
1553
1554 if (layer.compositionType == HWC_OVERLAY) {
1555 if (!layer.handle)
1556 continue;
1557
1558 ALOGV("HDMI video layer:");
1559 dump_layer(&layer);
1560
1561 exynos5_gsc_data_t &gsc = pdev->gsc[HDMI_GSC_IDX];
1562 int ret = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1,
1563 HAL_PIXEL_FORMAT_RGBX_8888, NULL);
1564 if (ret < 0) {
1565 ALOGE("failed to configure gscaler for video layer");
1566 continue;
1567 }
1568
1569 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf];
1570 private_handle_t *h = private_handle_t::dynamicCast(dst_buf);
1571
1572 int acquireFenceFd = gsc.dst_cfg.releaseFenceFd;
1573 int releaseFenceFd = -1;
1574
1575 hdmi_output(pdev, pdev->hdmi_layers[0], layer, h, acquireFenceFd,
1576 &releaseFenceFd);
1577 video_layer = &layer;
1578
1579 gsc.dst_buf_fence[gsc.current_buf] = releaseFenceFd;
1580 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS;
1581 }
1582
1583 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) {
1584 if (pdev->hdmi_fb_needed && layer.handle) {
1585 ALOGV("HDMI FB layer:");
1586 dump_layer(&layer);
1587
1588 private_handle_t *h = private_handle_t::dynamicCast(layer.handle);
1589 hdmi_show_layer(pdev, pdev->hdmi_layers[1]);
1590 hdmi_output(pdev, pdev->hdmi_layers[1], layer, h, layer.acquireFenceFd,
1591 &layer.releaseFenceFd);
1592 } else {
1593 hdmi_hide_layer(pdev, pdev->hdmi_layers[1]);
1594 }
1595 }
1596 }
1597
1598 if (!video_layer) {
1599 hdmi_disable_layer(pdev, pdev->hdmi_layers[0]);
1600 exynos5_cleanup_gsc_m2m(pdev, HDMI_GSC_IDX);
1601 }
1602
1603 if (exynos_v4l2_s_ctrl(pdev->hdmi_layers[1].fd, V4L2_CID_TV_UPDATE, 1) < 0) {
1604 ALOGE("%s: s_ctrl(CID_TV_UPDATE) failed %d", __func__, errno);
1605 return -1;
1606 }
1607
1608 return 0;
1609 }
1610
exynos5_set(struct hwc_composer_device_1 * dev,size_t numDisplays,hwc_display_contents_1_t ** displays)1611 static int exynos5_set(struct hwc_composer_device_1 *dev,
1612 size_t numDisplays, hwc_display_contents_1_t** displays)
1613 {
1614 if (!numDisplays || !displays)
1615 return 0;
1616
1617 exynos5_hwc_composer_device_1_t *pdev =
1618 (exynos5_hwc_composer_device_1_t *)dev;
1619 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY];
1620 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL];
1621 int fimd_err = 0, hdmi_err = 0;
1622
1623 if (fimd_contents)
1624 fimd_err = exynos5_set_fimd(pdev, fimd_contents);
1625
1626 if (hdmi_contents)
1627 hdmi_err = exynos5_set_hdmi(pdev, hdmi_contents);
1628
1629 if (fimd_err)
1630 return fimd_err;
1631
1632 return hdmi_err;
1633 }
1634
exynos5_registerProcs(struct hwc_composer_device_1 * dev,hwc_procs_t const * procs)1635 static void exynos5_registerProcs(struct hwc_composer_device_1* dev,
1636 hwc_procs_t const* procs)
1637 {
1638 struct exynos5_hwc_composer_device_1_t* pdev =
1639 (struct exynos5_hwc_composer_device_1_t*)dev;
1640 pdev->procs = procs;
1641 }
1642
exynos5_query(struct hwc_composer_device_1 * dev,int what,int * value)1643 static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value)
1644 {
1645 struct exynos5_hwc_composer_device_1_t *pdev =
1646 (struct exynos5_hwc_composer_device_1_t *)dev;
1647
1648 switch (what) {
1649 case HWC_BACKGROUND_LAYER_SUPPORTED:
1650 // we support the background layer
1651 value[0] = 1;
1652 break;
1653 case HWC_VSYNC_PERIOD:
1654 // vsync period in nanosecond
1655 value[0] = pdev->vsync_period;
1656 break;
1657 default:
1658 // unsupported query
1659 return -EINVAL;
1660 }
1661 return 0;
1662 }
1663
exynos5_eventControl(struct hwc_composer_device_1 * dev,int dpy,int event,int enabled)1664 static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy,
1665 int event, int enabled)
1666 {
1667 struct exynos5_hwc_composer_device_1_t *pdev =
1668 (struct exynos5_hwc_composer_device_1_t *)dev;
1669
1670 switch (event) {
1671 case HWC_EVENT_VSYNC:
1672 __u32 val = !!enabled;
1673 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val);
1674 if (err < 0) {
1675 ALOGE("vsync ioctl failed");
1676 return -errno;
1677 }
1678
1679 return 0;
1680 }
1681
1682 return -EINVAL;
1683 }
1684
handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t * pdev,const char * buff,int len)1685 static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev,
1686 const char *buff, int len)
1687 {
1688 const char *s = buff;
1689 s += strlen(s) + 1;
1690
1691 while (*s) {
1692 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE=")))
1693 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1;
1694
1695 s += strlen(s) + 1;
1696 if (s - buff >= len)
1697 break;
1698 }
1699
1700 if (pdev->hdmi_hpd) {
1701 if (hdmi_get_config(pdev)) {
1702 ALOGE("Error reading HDMI configuration");
1703 pdev->hdmi_hpd = false;
1704 return;
1705 }
1706
1707 pdev->hdmi_blanked = false;
1708 }
1709
1710 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled");
1711 if (pdev->hdmi_hpd)
1712 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w);
1713
1714 /* hwc_dev->procs is set right after the device is opened, but there is
1715 * still a race condition where a hotplug event might occur after the open
1716 * but before the procs are registered. */
1717 if (pdev->procs)
1718 pdev->procs->hotplug(pdev->procs, HWC_DISPLAY_EXTERNAL, pdev->hdmi_hpd);
1719 }
1720
handle_vsync_event(struct exynos5_hwc_composer_device_1_t * pdev)1721 static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev)
1722 {
1723 if (!pdev->procs)
1724 return;
1725
1726 int err = lseek(pdev->vsync_fd, 0, SEEK_SET);
1727 if (err < 0) {
1728 ALOGE("error seeking to vsync timestamp: %s", strerror(errno));
1729 return;
1730 }
1731
1732 char buf[4096];
1733 err = read(pdev->vsync_fd, buf, sizeof(buf));
1734 if (err < 0) {
1735 ALOGE("error reading vsync timestamp: %s", strerror(errno));
1736 return;
1737 }
1738 buf[sizeof(buf) - 1] = '\0';
1739
1740 errno = 0;
1741 uint64_t timestamp = strtoull(buf, NULL, 0);
1742 if (!errno)
1743 pdev->procs->vsync(pdev->procs, 0, timestamp);
1744 }
1745
hwc_vsync_thread(void * data)1746 static void *hwc_vsync_thread(void *data)
1747 {
1748 struct exynos5_hwc_composer_device_1_t *pdev =
1749 (struct exynos5_hwc_composer_device_1_t *)data;
1750 char uevent_desc[4096];
1751 memset(uevent_desc, 0, sizeof(uevent_desc));
1752
1753 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
1754
1755 uevent_init();
1756
1757 char temp[4096];
1758 int err = read(pdev->vsync_fd, temp, sizeof(temp));
1759 if (err < 0) {
1760 ALOGE("error reading vsync timestamp: %s", strerror(errno));
1761 return NULL;
1762 }
1763
1764 struct pollfd fds[2];
1765 fds[0].fd = pdev->vsync_fd;
1766 fds[0].events = POLLPRI;
1767 fds[1].fd = uevent_get_fd();
1768 fds[1].events = POLLIN;
1769
1770 while (true) {
1771 int err = poll(fds, 2, -1);
1772
1773 if (err > 0) {
1774 if (fds[0].revents & POLLPRI) {
1775 handle_vsync_event(pdev);
1776 }
1777 else if (fds[1].revents & POLLIN) {
1778 int len = uevent_next_event(uevent_desc,
1779 sizeof(uevent_desc) - 2);
1780
1781 bool hdmi = !strcmp(uevent_desc,
1782 "change@/devices/virtual/switch/hdmi");
1783 if (hdmi)
1784 handle_hdmi_uevent(pdev, uevent_desc, len);
1785 }
1786 }
1787 else if (err == -1) {
1788 if (errno == EINTR)
1789 break;
1790 ALOGE("error in vsync thread: %s", strerror(errno));
1791 }
1792 }
1793
1794 return NULL;
1795 }
1796
exynos5_blank(struct hwc_composer_device_1 * dev,int disp,int blank)1797 static int exynos5_blank(struct hwc_composer_device_1 *dev, int disp, int blank)
1798 {
1799 struct exynos5_hwc_composer_device_1_t *pdev =
1800 (struct exynos5_hwc_composer_device_1_t *)dev;
1801
1802 switch (disp) {
1803 case HWC_DISPLAY_PRIMARY: {
1804 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK;
1805 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank);
1806 if (err < 0) {
1807 if (errno == EBUSY)
1808 ALOGI("%sblank ioctl failed (display already %sblanked)",
1809 blank ? "" : "un", blank ? "" : "un");
1810 else
1811 ALOGE("%sblank ioctl failed: %s", blank ? "" : "un",
1812 strerror(errno));
1813 return -errno;
1814 }
1815 break;
1816 }
1817
1818 case HWC_DISPLAY_EXTERNAL:
1819 if (pdev->hdmi_hpd) {
1820 if (blank && !pdev->hdmi_blanked)
1821 hdmi_disable(pdev);
1822 pdev->hdmi_blanked = !!blank;
1823 }
1824 break;
1825
1826 default:
1827 return -EINVAL;
1828
1829 }
1830
1831 return 0;
1832 }
1833
exynos5_dump(hwc_composer_device_1 * dev,char * buff,int buff_len)1834 static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len)
1835 {
1836 if (buff_len <= 0)
1837 return;
1838
1839 struct exynos5_hwc_composer_device_1_t *pdev =
1840 (struct exynos5_hwc_composer_device_1_t *)dev;
1841
1842 android::String8 result;
1843
1844 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled);
1845 if (pdev->hdmi_enabled)
1846 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h);
1847 result.append(
1848 " type | handle | color | blend | format | position | size | gsc \n"
1849 "----------+----------|----------+-------+--------+---------------+---------------------\n");
1850 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n"
1851
1852 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) {
1853 struct s3c_fb_win_config &config = pdev->last_config[i];
1854 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) {
1855 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s",
1856 "DISABLED", "-", "-", "-", "-", "-", "-");
1857 }
1858 else {
1859 if (config.state == config.S3C_FB_WIN_STATE_COLOR)
1860 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR",
1861 "-", config.color, "-", "-");
1862 else
1863 result.appendFormat(" %8s | %8x | %8s | %5x | %6x",
1864 pdev->last_fb_window == i ? "FB" : "OVERLAY",
1865 intptr_t(pdev->last_handles[i]),
1866 "-", config.blending, config.format);
1867
1868 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y,
1869 config.w, config.h);
1870 }
1871 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE)
1872 result.appendFormat(" | %3s", "-");
1873 else
1874 result.appendFormat(" | %3d",
1875 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]);
1876 result.append("\n");
1877 }
1878
1879 strlcpy(buff, result.string(), buff_len);
1880 }
1881
exynos5_getDisplayConfigs(struct hwc_composer_device_1 * dev,int disp,uint32_t * configs,size_t * numConfigs)1882 static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev,
1883 int disp, uint32_t *configs, size_t *numConfigs)
1884 {
1885 struct exynos5_hwc_composer_device_1_t *pdev =
1886 (struct exynos5_hwc_composer_device_1_t *)dev;
1887
1888 if (*numConfigs == 0)
1889 return 0;
1890
1891 if (disp == HWC_DISPLAY_PRIMARY) {
1892 configs[0] = 0;
1893 *numConfigs = 1;
1894 return 0;
1895 } else if (disp == HWC_DISPLAY_EXTERNAL) {
1896 if (!pdev->hdmi_hpd) {
1897 return -EINVAL;
1898 }
1899
1900 int err = hdmi_get_config(pdev);
1901 if (err) {
1902 return -EINVAL;
1903 }
1904
1905 configs[0] = 0;
1906 *numConfigs = 1;
1907 return 0;
1908 }
1909
1910 return -EINVAL;
1911 }
1912
exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t * pdev,const uint32_t attribute)1913 static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev,
1914 const uint32_t attribute)
1915 {
1916 switch(attribute) {
1917 case HWC_DISPLAY_VSYNC_PERIOD:
1918 return pdev->vsync_period;
1919
1920 case HWC_DISPLAY_WIDTH:
1921 return pdev->xres;
1922
1923 case HWC_DISPLAY_HEIGHT:
1924 return pdev->yres;
1925
1926 case HWC_DISPLAY_DPI_X:
1927 return pdev->xdpi;
1928
1929 case HWC_DISPLAY_DPI_Y:
1930 return pdev->ydpi;
1931
1932 default:
1933 ALOGE("unknown display attribute %u", attribute);
1934 return -EINVAL;
1935 }
1936 }
1937
exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t * pdev,const uint32_t attribute)1938 static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev,
1939 const uint32_t attribute)
1940 {
1941 switch(attribute) {
1942 case HWC_DISPLAY_VSYNC_PERIOD:
1943 return pdev->vsync_period;
1944
1945 case HWC_DISPLAY_WIDTH:
1946 return pdev->hdmi_w;
1947
1948 case HWC_DISPLAY_HEIGHT:
1949 return pdev->hdmi_h;
1950
1951 case HWC_DISPLAY_DPI_X:
1952 case HWC_DISPLAY_DPI_Y:
1953 return 0; // unknown
1954
1955 default:
1956 ALOGE("unknown display attribute %u", attribute);
1957 return -EINVAL;
1958 }
1959 }
1960
exynos5_getDisplayAttributes(struct hwc_composer_device_1 * dev,int disp,uint32_t config,const uint32_t * attributes,int32_t * values)1961 static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev,
1962 int disp, uint32_t config, const uint32_t *attributes, int32_t *values)
1963 {
1964 struct exynos5_hwc_composer_device_1_t *pdev =
1965 (struct exynos5_hwc_composer_device_1_t *)dev;
1966
1967 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) {
1968 if (disp == HWC_DISPLAY_PRIMARY)
1969 values[i] = exynos5_fimd_attribute(pdev, attributes[i]);
1970 else if (disp == HWC_DISPLAY_EXTERNAL)
1971 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]);
1972 else {
1973 ALOGE("unknown display type %u", disp);
1974 return -EINVAL;
1975 }
1976 }
1977
1978 return 0;
1979 }
1980
1981 static int exynos5_close(hw_device_t* device);
1982
exynos5_open(const struct hw_module_t * module,const char * name,struct hw_device_t ** device)1983 static int exynos5_open(const struct hw_module_t *module, const char *name,
1984 struct hw_device_t **device)
1985 {
1986 int ret;
1987 int refreshRate;
1988 int sw_fd;
1989
1990 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
1991 return -EINVAL;
1992 }
1993
1994 struct exynos5_hwc_composer_device_1_t *dev;
1995 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev));
1996 memset(dev, 0, sizeof(*dev));
1997
1998 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID,
1999 (const struct hw_module_t **)&dev->gralloc_module)) {
2000 ALOGE("failed to get gralloc hw module");
2001 ret = -EINVAL;
2002 goto err_get_module;
2003 }
2004
2005 if (gralloc_open((const hw_module_t *)dev->gralloc_module,
2006 &dev->alloc_device)) {
2007 ALOGE("failed to open gralloc");
2008 ret = -EINVAL;
2009 goto err_get_module;
2010 }
2011
2012 dev->fd = open("/dev/graphics/fb0", O_RDWR);
2013 if (dev->fd < 0) {
2014 ALOGE("failed to open framebuffer");
2015 ret = dev->fd;
2016 goto err_open_fb;
2017 }
2018
2019 struct fb_var_screeninfo info;
2020 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) {
2021 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno));
2022 ret = -errno;
2023 goto err_ioctl;
2024 }
2025
2026 refreshRate = 1000000000000LLU /
2027 (
2028 uint64_t( info.upper_margin + info.lower_margin + info.yres )
2029 * ( info.left_margin + info.right_margin + info.xres )
2030 * info.pixclock
2031 );
2032
2033 if (refreshRate == 0) {
2034 ALOGW("invalid refresh rate, assuming 60 Hz");
2035 refreshRate = 60;
2036 }
2037
2038 dev->xres = 2560;
2039 dev->yres = 1600;
2040 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width;
2041 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height;
2042 dev->vsync_period = 1000000000 / refreshRate;
2043
2044 ALOGV("using\n"
2045 "xres = %d px\n"
2046 "yres = %d px\n"
2047 "width = %d mm (%f dpi)\n"
2048 "height = %d mm (%f dpi)\n"
2049 "refresh rate = %d Hz\n",
2050 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0,
2051 info.height, dev->ydpi / 1000.0, refreshRate);
2052
2053 for (size_t i = 0; i < NUM_GSC_UNITS; i++)
2054 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++)
2055 dev->gsc[i].dst_buf_fence[j] = -1;
2056
2057 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR);
2058 if (dev->hdmi_mixer0 < 0) {
2059 ALOGE("failed to open hdmi mixer0 subdev");
2060 ret = dev->hdmi_mixer0;
2061 goto err_ioctl;
2062 }
2063
2064 dev->hdmi_layers[0].id = 0;
2065 dev->hdmi_layers[0].fd = open("/dev/video16", O_RDWR);
2066 if (dev->hdmi_layers[0].fd < 0) {
2067 ALOGE("failed to open hdmi layer0 device");
2068 ret = dev->hdmi_layers[0].fd;
2069 goto err_mixer0;
2070 }
2071
2072 dev->hdmi_layers[1].id = 1;
2073 dev->hdmi_layers[1].fd = open("/dev/video17", O_RDWR);
2074 if (dev->hdmi_layers[1].fd < 0) {
2075 ALOGE("failed to open hdmi layer1 device");
2076 ret = dev->hdmi_layers[1].fd;
2077 goto err_hdmi0;
2078 }
2079
2080 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY);
2081 if (dev->vsync_fd < 0) {
2082 ALOGE("failed to open vsync attribute");
2083 ret = dev->vsync_fd;
2084 goto err_hdmi1;
2085 }
2086
2087 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY);
2088 if (sw_fd) {
2089 char val;
2090 if (read(sw_fd, &val, 1) == 1 && val == '1') {
2091 dev->hdmi_hpd = true;
2092 if (hdmi_get_config(dev)) {
2093 ALOGE("Error reading HDMI configuration");
2094 dev->hdmi_hpd = false;
2095 }
2096 }
2097 }
2098
2099 dev->base.common.tag = HARDWARE_DEVICE_TAG;
2100 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1;
2101 dev->base.common.module = const_cast<hw_module_t *>(module);
2102 dev->base.common.close = exynos5_close;
2103
2104 dev->base.prepare = exynos5_prepare;
2105 dev->base.set = exynos5_set;
2106 dev->base.eventControl = exynos5_eventControl;
2107 dev->base.blank = exynos5_blank;
2108 dev->base.query = exynos5_query;
2109 dev->base.registerProcs = exynos5_registerProcs;
2110 dev->base.dump = exynos5_dump;
2111 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs;
2112 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes;
2113
2114 *device = &dev->base.common;
2115
2116 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev);
2117 if (ret) {
2118 ALOGE("failed to start vsync thread: %s", strerror(ret));
2119 ret = -ret;
2120 goto err_vsync;
2121 }
2122
2123 char value[PROPERTY_VALUE_MAX];
2124 property_get("debug.hwc.force_gpu", value, "0");
2125 dev->force_gpu = atoi(value);
2126
2127 return 0;
2128
2129 err_vsync:
2130 close(dev->vsync_fd);
2131 err_mixer0:
2132 close(dev->hdmi_mixer0);
2133 err_hdmi1:
2134 close(dev->hdmi_layers[0].fd);
2135 err_hdmi0:
2136 close(dev->hdmi_layers[1].fd);
2137 err_ioctl:
2138 close(dev->fd);
2139 err_open_fb:
2140 gralloc_close(dev->alloc_device);
2141 err_get_module:
2142 free(dev);
2143 return ret;
2144 }
2145
exynos5_close(hw_device_t * device)2146 static int exynos5_close(hw_device_t *device)
2147 {
2148 struct exynos5_hwc_composer_device_1_t *dev =
2149 (struct exynos5_hwc_composer_device_1_t *)device;
2150 pthread_kill(dev->vsync_thread, SIGTERM);
2151 pthread_join(dev->vsync_thread, NULL);
2152 for (size_t i = 0; i < NUM_GSC_UNITS; i++)
2153 exynos5_cleanup_gsc_m2m(dev, i);
2154 gralloc_close(dev->alloc_device);
2155 close(dev->vsync_fd);
2156 close(dev->hdmi_mixer0);
2157 close(dev->hdmi_layers[0].fd);
2158 close(dev->hdmi_layers[1].fd);
2159 close(dev->fd);
2160 return 0;
2161 }
2162
2163 static struct hw_module_methods_t exynos5_hwc_module_methods = {
2164 open: exynos5_open,
2165 };
2166
2167 hwc_module_t HAL_MODULE_INFO_SYM = {
2168 common: {
2169 tag: HARDWARE_MODULE_TAG,
2170 module_api_version: HWC_MODULE_API_VERSION_0_1,
2171 hal_api_version: HARDWARE_HAL_API_VERSION,
2172 id: HWC_HARDWARE_MODULE_ID,
2173 name: "Samsung exynos5 hwcomposer module",
2174 author: "Google",
2175 methods: &exynos5_hwc_module_methods,
2176 }
2177 };
2178