Lines Matching refs:Rd
1004 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1011 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1012 iii, opc, "\t$Rd, $Rn, $imm",
1013 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
1014 bits<4> Rd;
1019 let Inst{15-12} = Rd;
1023 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1024 iir, opc, "\t$Rd, $Rn, $Rm",
1025 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1026 bits<4> Rd;
1032 let Inst{15-12} = Rd;
1037 def rsi : AsI1<opcod, (outs GPR:$Rd),
1039 iis, opc, "\t$Rd, $Rn, $shift",
1040 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1041 bits<4> Rd;
1046 let Inst{15-12} = Rd;
1052 def rsr : AsI1<opcod, (outs GPR:$Rd),
1054 iis, opc, "\t$Rd, $Rn, $shift",
1055 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1056 bits<4> Rd;
1061 let Inst{15-12} = Rd;
1073 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1080 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1081 iii, opc, "\t$Rd, $Rn, $imm",
1082 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1083 bits<4> Rd;
1088 let Inst{15-12} = Rd;
1092 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1093 iir, opc, "\t$Rd, $Rn, $Rm",
1095 bits<4> Rd;
1101 let Inst{15-12} = Rd;
1105 def rsi : AsI1<opcod, (outs GPR:$Rd),
1107 iis, opc, "\t$Rd, $Rn, $shift",
1108 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1109 bits<4> Rd;
1114 let Inst{15-12} = Rd;
1120 def rsr : AsI1<opcod, (outs GPR:$Rd),
1122 iis, opc, "\t$Rd, $Rn, $shift",
1123 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1124 bits<4> Rd;
1129 let Inst{15-12} = Rd;
1146 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1148 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1150 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1155 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1158 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1161 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1164 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1175 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1177 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1179 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1182 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1185 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1188 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1270 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1271 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1272 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1274 bits<4> Rd;
1278 let Inst{15-12} = Rd;
1284 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1285 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1295 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1296 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1297 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1300 bits<4> Rd;
1305 let Inst{15-12} = Rd;
1312 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1313 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1322 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1326 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1327 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1328 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1330 bits<4> Rd;
1334 let Inst{15-12} = Rd;
1338 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1339 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1340 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1342 bits<4> Rd;
1349 let Inst{15-12} = Rd;
1352 def rsi : AsI1<opcod, (outs GPR:$Rd),
1354 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1355 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1357 bits<4> Rd;
1362 let Inst{15-12} = Rd;
1367 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1369 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1370 [(set GPRnopc:$Rd, CPSR,
1373 bits<4> Rd;
1378 let Inst{15-12} = Rd;
1389 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1392 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1393 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1394 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1396 bits<4> Rd;
1400 let Inst{15-12} = Rd;
1404 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1405 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1407 bits<4> Rd;
1413 let Inst{15-12} = Rd;
1416 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1417 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1418 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1420 bits<4> Rd;
1425 let Inst{15-12} = Rd;
1430 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1431 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1432 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1434 bits<4> Rd;
1439 let Inst{15-12} = Rd;
1657 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1658 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1659 bits<4> Rd;
1663 let Inst{15-12} = Rd;
1844 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1845 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1846 bits<4> Rd;
1854 let Inst{15-12} = Rd;
1859 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1862 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2203 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2205 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2890 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2891 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2892 bits<4> Rd;
2899 let Inst{15-12} = Rd;
2904 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2905 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2906 bits<4> Rd;
2912 let Inst{15-12} = Rd;
2915 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2917 "mov", "\t$Rd, $src",
2918 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2919 bits<4> Rd;
2921 let Inst{15-12} = Rd;
2931 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2933 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2935 bits<4> Rd;
2937 let Inst{15-12} = Rd;
2946 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2947 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2948 bits<4> Rd;
2951 let Inst{15-12} = Rd;
2957 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2959 "movw", "\t$Rd, $imm",
2960 [(set GPR:$Rd, imm0_65535:$imm)]>,
2962 bits<4> Rd;
2964 let Inst{15-12} = Rd;
2972 def : InstAlias<"mov${p} $Rd, $imm",
2973 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2976 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2979 let Constraints = "$src = $Rd" in {
2980 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2983 "movt", "\t$Rd, $imm",
2984 [(set GPRnopc:$Rd,
2988 bits<4> Rd;
2990 let Inst{15-12} = Rd;
2998 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3007 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3008 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3072 def SBFX : I<(outs GPRnopc:$Rd),
3075 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3077 bits<4> Rd;
3084 let Inst{15-12} = Rd;
3089 def UBFX : I<(outs GPR:$Rd),
3092 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3094 bits<4> Rd;
3101 let Inst{15-12} = Rd;
3185 string asm = "\t$Rd, $Rn, $Rm">
3186 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3188 bits<4> Rd;
3193 let Inst{15-12} = Rd;
3202 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3203 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3205 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3206 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3209 "\t$Rd, $Rm, $Rn">;
3212 "\t$Rd, $Rm, $Rn">;
3259 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3261 "\t$Rd, $Rn, $Rm", []>,
3263 bits<4> Rd;
3269 let Inst{19-16} = Rd;
3273 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3275 "\t$Rd, $Rn, $Rm, $Ra", []>,
3277 bits<4> Rd;
3283 let Inst{19-16} = Rd;
3291 def SSAT : AI<(outs GPRnopc:$Rd),
3293 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3294 bits<4> Rd;
3301 let Inst{15-12} = Rd;
3307 def SSAT16 : AI<(outs GPRnopc:$Rd),
3309 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3310 bits<4> Rd;
3315 let Inst{15-12} = Rd;
3320 def USAT : AI<(outs GPRnopc:$Rd),
3322 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3323 bits<4> Rd;
3329 let Inst{15-12} = Rd;
3336 def USAT16 : AI<(outs GPRnopc:$Rd),
3338 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3339 bits<4> Rd;
3344 let Inst{15-12} = Rd;
3375 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3377 "bfc", "\t$Rd, $imm", "$src = $Rd",
3378 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3380 bits<4> Rd;
3384 let Inst{15-12} = Rd;
3390 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3392 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3393 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3396 bits<4> Rd;
3401 let Inst{15-12} = Rd;
3407 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3408 "mvn", "\t$Rd, $Rm",
3409 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3410 bits<4> Rd;
3415 let Inst{15-12} = Rd;
3418 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3419 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3420 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3421 bits<4> Rd;
3425 let Inst{15-12} = Rd;
3430 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3431 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3432 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3433 bits<4> Rd;
3437 let Inst{15-12} = Rd;
3445 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3446 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3447 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3448 bits<4> Rd;
3452 let Inst{15-12} = Rd;
3465 bits<4> Rd;
3468 let Inst{19-16} = Rd;
3500 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3501 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3503 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3504 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3510 let Constraints = "@earlyclobber $Rd" in
3511 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3514 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3515 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3519 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3520 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3521 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3527 let Constraints = "@earlyclobber $Rd" in
3528 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3531 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3532 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3535 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3536 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3537 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3539 bits<4> Rd;
3543 let Inst{19-16} = Rd;
3627 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3628 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3629 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3634 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3635 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3640 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3642 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3643 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3646 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3648 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3651 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3653 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3656 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3658 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3662 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3663 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3664 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3668 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3669 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3670 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3674 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3675 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3676 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3680 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3681 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3682 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3686 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3687 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3688 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3692 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3693 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3694 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3702 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3704 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3705 [(set GPRnopc:$Rd, (add GPR:$Ra,
3710 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3712 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3713 [(set GPRnopc:$Rd,
3718 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3720 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3721 [(set GPRnopc:$Rd,
3726 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3728 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3729 [(set GPRnopc:$Rd,
3734 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3736 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3737 [(set GPRnopc:$Rd,
3742 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3744 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3745 [(set GPRnopc:$Rd,
3795 bits<4> Rd;
3797 let Inst{19-16} = Rd;
3803 bits<4> Rd;
3804 let Inst{19-16} = Rd;
3818 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3820 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3822 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3824 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3841 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3842 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3843 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3844 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3853 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3854 "sdiv", "\t$Rd, $Rn, $Rm",
3855 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3858 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3859 "udiv", "\t$Rd, $Rn, $Rm",
3860 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3867 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3868 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3869 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3871 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3872 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3873 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3876 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3877 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3878 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3881 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3882 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3883 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3887 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3888 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3889 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3896 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3898 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3899 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3912 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3914 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3915 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4055 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4057 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4058 RegConstraint<"$false = $Rd">;
4060 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4063 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4065 RegConstraint<"$false = $Rd">;
4066 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4069 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4071 RegConstraint<"$false = $Rd">;
4075 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4079 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4082 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4085 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4086 RegConstraint<"$false = $Rd">;
4090 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4092 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4095 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4098 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4099 RegConstraint<"$false = $Rd">;
4288 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4289 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4290 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4291 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4292 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4293 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4294 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4296 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4298 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4677 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4678 "mrs", "\t$Rd, apsr", []> {
4679 bits<4> Rd;
4683 let Inst{15-12} = Rd;
4689 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4694 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4695 "mrs", "\t$Rd, spsr", []> {
4696 bits<4> Rd;
4700 let Inst{15-12} = Rd;
5028 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5029 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5031 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5032 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5040 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5041 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5042 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5043 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5047 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5048 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5049 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5050 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5051 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5052 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5053 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5054 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5055 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5056 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5057 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5058 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5060 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5061 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5062 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5063 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5064 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5065 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5066 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5067 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5068 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5069 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5070 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5071 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5111 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5113 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5114 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5115 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5116 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5118 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5119 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5124 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5125 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5131 // Likewise, "add Rd, so_imm_neg" -> sub
5132 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5133 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5134 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5135 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5137 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5138 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5139 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5140 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5147 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5148 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5149 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5151 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5152 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5154 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5155 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5157 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5158 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5161 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5162 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5163 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5164 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5165 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5167 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5168 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5170 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5171 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5173 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5174 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5179 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5180 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;