Lines Matching refs:Rm
1023 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1024 iir, opc, "\t$Rd, $Rn, $Rm",
1025 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1028 bits<4> Rm;
1034 let Inst{3-0} = Rm;
1092 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1093 iir, opc, "\t$Rd, $Rn, $Rm",
1097 bits<4> Rm;
1100 let Inst{3-0} = Rm;
1150 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1213 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1214 opc, "\t$Rn, $Rm",
1215 [(opnode GPR:$Rn, GPR:$Rm)]> {
1217 bits<4> Rm;
1224 let Inst{3-0} = Rm;
1270 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1271 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1272 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1275 bits<4> Rm;
1280 let Inst{3-0} = Rm;
1284 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1285 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1295 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1296 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1298 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1301 bits<4> Rm;
1308 let Inst{3-0} = Rm;
1312 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1313 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1338 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1339 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1340 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1344 bits<4> Rm;
1348 let Inst{3-0} = Rm;
1404 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1405 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1409 bits<4> Rm;
1412 let Inst{3-0} = Rm;
1657 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1658 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1661 bits<4> Rm;
1662 let Inst{3-0} = Rm;
2243 // {11-0} imm12/Rm
2260 // {11-0} imm12/Rm
2287 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2290 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2302 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2305 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2322 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2325 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2337 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2340 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2354 // {11-0} imm12/Rm
2373 // {11-0} imm12/Rm
2390 // {11-0} imm12/Rm
2409 // {11-0} imm12/Rm
2433 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2435 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2436 bits<5> Rm;
2437 let Inst{23} = Rm{4};
2441 let Inst{3-0} = Rm{3-0};
2503 // {11-0} imm12/Rm
2521 // {11-0} imm12/Rm
2599 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2602 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2617 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2620 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2632 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2635 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2649 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2652 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2665 // {11-0} imm12/Rm
2684 // {11-0} imm12/Rm
2702 // {11-0} imm12/Rm
2721 // {11-0} imm12/Rm
2747 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2749 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2750 bits<5> Rm;
2751 let Inst{23} = Rm{4};
2754 let Inst{3-0} = Rm{3-0};
2890 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2891 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2893 bits<4> Rm;
2898 let Inst{3-0} = Rm;
2904 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2905 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2907 bits<4> Rm;
2911 let Inst{3-0} = Rm;
3007 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3008 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3184 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3185 string asm = "\t$Rd, $Rn, $Rm">
3189 bits<4> Rm;
3194 let Inst{3-0} = Rm;
3202 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3203 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3205 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3206 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3208 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3209 "\t$Rd, $Rm, $Rn">;
3211 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3212 "\t$Rd, $Rm, $Rn">;
3259 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3261 "\t$Rd, $Rn, $Rm", []>,
3265 bits<4> Rm;
3270 let Inst{11-8} = Rm;
3273 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3275 "\t$Rd, $Rn, $Rm, $Ra", []>,
3279 bits<4> Rm;
3285 let Inst{11-8} = Rm;
3407 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3408 "mvn", "\t$Rd, $Rm",
3409 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3411 bits<4> Rm;
3416 let Inst{3-0} = Rm;
3466 bits<4> Rm;
3469 let Inst{11-8} = Rm;
3477 bits<4> Rm;
3481 let Inst{11-8} = Rm;
3489 bits<4> Rm;
3493 let Inst{11-8} = Rm;
3502 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3503 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3504 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3511 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3514 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3515 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3519 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3520 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3521 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3529 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3531 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3532 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3535 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3536 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3537 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3540 bits<4> Rm;
3545 let Inst{11-8} = Rm;
3553 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3554 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3558 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3559 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3564 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3566 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3570 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3572 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3579 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3580 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3583 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3584 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3588 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3589 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3593 bits<4> Rm;
3597 let Inst{11-8} = Rm;
3603 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3605 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3609 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3611 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3618 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3620 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3627 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3628 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3629 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3634 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3635 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3641 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3642 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3643 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3647 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3648 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3652 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3653 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3657 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3658 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3662 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3663 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3665 (sext_inreg GPR:$Rm, i16)))]>,
3668 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3669 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3671 (sra GPR:$Rm, (i32 16))))]>,
3674 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3675 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3677 (sext_inreg GPR:$Rm, i16)))]>,
3680 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3681 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3683 (sra GPR:$Rm, (i32 16))))]>,
3686 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3687 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3689 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3692 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3693 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3695 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3703 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3704 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3707 (sext_inreg GPRnopc:$Rm, i16))))]>,
3711 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3712 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3715 (sra GPRnopc:$Rm, (i32 16)))))]>,
3719 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3720 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3723 (sext_inreg GPRnopc:$Rm, i16))))]>,
3727 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3728 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3731 (sra GPRnopc:$Rm, (i32 16)))))]>,
3735 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3736 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3739 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3743 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3744 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3747 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3757 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3758 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3762 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3763 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3767 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3768 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3772 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3773 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3781 bits<4> Rm;
3785 let Inst{11-8} = Rm;
3819 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3820 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3823 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3824 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3828 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3831 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3832 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3841 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3842 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3843 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3844 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3853 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3854 "sdiv", "\t$Rd, $Rn, $Rm",
3855 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3858 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3859 "udiv", "\t$Rd, $Rn, $Rm",
3860 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3867 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3868 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3869 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3871 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3872 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3873 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3876 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3877 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3878 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3881 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3882 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3883 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3887 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3888 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3889 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3892 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3893 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3894 (REVSH GPR:$Rm)>;
3897 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3898 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3900 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3905 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3906 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3907 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3908 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3913 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3914 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3916 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3964 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3965 "cmn", "\t$Rn, $Rm",
3967 GPR:$Rn, GPR:$Rm)]> {
3969 bits<4> Rm;
3976 let Inst{3-0} = Rm;
4055 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4057 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4945 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4946 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4947 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4948 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4954 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4955 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4956 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4957 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5028 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5029 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5031 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5032 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5047 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5048 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5049 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5050 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5051 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5052 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5053 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5054 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5055 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5056 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5057 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5058 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5060 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5061 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5062 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5063 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5064 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5065 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5066 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5067 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5068 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5069 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5070 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5071 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5147 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5148 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5149 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5151 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5152 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5154 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5155 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5157 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5158 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5161 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5162 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5164 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5165 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5167 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5168 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5170 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5171 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5173 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5174 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5179 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5180 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5189 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5190 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5192 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5193 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,