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Lines Matching refs:ry

139   MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
196 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
197 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
201 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
211 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
212 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
218 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
219 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
226 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
227 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
269 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
270 !strconcat(asmstr, "\t$rx, $ry"), []>;
276 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
277 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
286 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
287 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
291 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
296 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
297 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
303 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
304 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
307 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
308 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
318 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
319 !strconcat(asmstr, "\t$rz, $ry"),
341 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
342 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
522 // Format: ADDU rz, rx, ry MIPS16e
530 // Format: AND rx, ry MIPS16e
618 // Format: CMP rx, ry MIPS16e
646 // Format: DIV rx, ry MIPS16e
655 // Format: DIVU rx, ry MIPS16e
705 // Format: LB ry, offset(rx) MIPS16e
714 // Format: LBU ry, offset(rx) MIPS16e
724 // Format: LH ry, offset(rx) MIPS16e
733 // Format: LHU ry, offset(rx) MIPS16e
757 // Format: LW ry, offset(rx) MIPS16e
781 // Format: MOVE ry, r32 MIPS16e
823 // Format: MULT rx, ry MIPS16e
834 // Format: MULTU rx, ry MIPS16e
845 // Format: NEG rx, ry MIPS16e
852 // Format: NOT rx, ry MIPS16e
859 // Format: OR rx, ry MIPS16e
928 // Format: SB ry, offset(rx) MIPS16e
1050 // Format: SH ry, offset(rx) MIPS16e
1058 // Format: SLL rx, ry, sa MIPS16e
1065 // Format: SLLV ry, rx MIPS16e
1118 // Format: SLT rx, ry MIPS16e
1128 // Format: SLTU rx, ry MIPS16e
1144 // Format: SRAV ry, rx MIPS16e
1153 // Format: SRA rx, ry, sa MIPS16e
1162 // Format: SRLV ry, rx MIPS16e
1171 // Format: SRL rx, ry, sa MIPS16e
1179 // Format: SUBU rz, rx, ry MIPS16e
1186 // Format: SW ry, offset(rx) MIPS16e
1202 // Format: XOR rx, ry MIPS16e
1301 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1302 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1345 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1346 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1364 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1365 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1372 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1373 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1387 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1388 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1400 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1401 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1408 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1409 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1436 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1437 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1444 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1445 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1453 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1454 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1469 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1470 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1476 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1477 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;