Lines Matching refs:BaseReg
167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
170 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
185 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
200 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
201 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
307 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
310 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode in EmitMemModRMByte()
335 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; in EmitMemModRMByte()
350 (!is64BitMode() || BaseReg != 0)) { in EmitMemModRMByte()
352 if (BaseReg == 0) { // [disp32] in X86-32 mode in EmitMemModRMByte()
387 if (BaseReg == 0) { in EmitMemModRMByte()
415 if (BaseReg == 0) { in EmitMemModRMByte()