| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 341 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
346 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
351 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
357 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
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| D | ARMISelDAGToDAG.cpp | 118 SDValue &Opc) { in SelectAddrMode2Base()
123 SDValue &Opc) { in SelectAddrMode2ShOp()
128 SDValue &Opc) { in SelectAddrMode2()
308 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
476 SDValue &Opc, in SelectImmShifterOperand()
500 SDValue &Opc, in SelectRegShifterOperand()
576 SDValue &Opc) { in SelectLdStSOReg()
675 SDValue &Opc) { in SelectAddrMode2Worker()
809 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
845 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
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| D | ARMFastISel.cpp | 522 unsigned Opc; in ARMMaterializeFP() local
548 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
567 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
583 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
637 unsigned Opc; in ARMMaterializeGV() local
674 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; in ARMMaterializeGV() local
689 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
756 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in TargetMaterializeAlloca() local
938 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
1006 unsigned Opc; in ARMEmitLoad() local
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| D | ARMInstrInfo.cpp | 122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? in runOnMachineFunction() local
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| D | Thumb2InstrInfo.cpp | 226 unsigned Opc = 0; in emitT2RegPlusImmediate() local
568 unsigned Opc = MI->getOpcode(); in getITInstrPredicate() local
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| D | Thumb1RegisterInfo.cpp | 129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); in emitThumbRegPlusImmInReg() local
143 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, in calcNumMI()
182 int Opc = 0; in emitThumbRegPlusImmediate() local
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| D | ARMLoadStoreOptimizer.cpp | 262 static bool isT2i32Load(unsigned Opc) { in isT2i32Load()
266 static bool isi32Load(unsigned Opc) { in isi32Load()
270 static bool isT2i32Store(unsigned Opc) { in isT2i32Store()
274 static bool isi32Store(unsigned Opc) { in isi32Store()
631 static unsigned getUpdatingLSMultipleOpcode(unsigned Opc, in getUpdatingLSMultipleOpcode()
793 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc, in getPreIndexedLoadStoreOpcode()
818 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc, in getPostIndexedLoadStoreOpcode()
1825 int Opc = MI->getOpcode(); in RescheduleLoadStoreInstrs() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 54 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
60 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
107 int Opc = MI->getOpcode(); in runOnMachineFunction() local
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| D | HexagonExpandPredSpillCode.cpp | 77 int Opc = MI->getOpcode(); in runOnMachineFunction() local
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| D | HexagonInstrInfo.cpp | 315 unsigned Opc = MI->getOpcode(); in analyzeCompare() local
922 const int Opc = MI->getOpcode(); in isPredicable() local
1472 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { in getMatchingCondBranchOpcode()
1712 int Opc = MI->getOpcode(); in PredicateInstruction() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 44 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
69 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
89 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
163 unsigned Opc = 0; in storeRegToStackSlot() local
190 unsigned Opc = 0; in loadRegFromStackSlot() local
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| D | MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd; member
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| D | Mips16InstrInfo.cpp | 72 unsigned Opc = 0; in copyPhysReg() local
108 unsigned Opc = 0; in storeRegToStackSlot() local
124 unsigned Opc = 0; in loadRegFromStackSlot() local
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| D | Mips16ISelDAGToDAG.cpp | 40 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty, in selectMULT()
248 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectNode() local
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| D | MipsInstrInfo.cpp | 77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, in AnalyzeCondBr()
107 unsigned Opc = Cond[0].getImm(); in BuildCondBr() local
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| D | MipsSEISelDAGToDAG.cpp | 182 MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty, in selectMULT()
204 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectAddESubE() local
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| D | MipsSEISelLowering.cpp | 42 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in MipsSETargetLowering() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 1730 unsigned Opc = Orig->getOpcode(); in reMaterialize() local
1790 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() in convertToThreeAddressWithLEA() local
1967 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2000 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
2027 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
2054 unsigned Opc; in convertToThreeAddress() local
2122 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2168 unsigned Opc; in commuteInstruction() local
2205 unsigned Opc; in commuteInstruction() local
2293 static X86::CondCode getCondFromSETOpc(unsigned Opc) { in getCondFromSETOpc()
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| D | X86FrameLowering.cpp | 107 unsigned Opc = MBBI->getOpcode(); in findDeadCallerSavedReg() local
152 unsigned Opc; in emitSPUpdate() local
209 unsigned Opc = PI->getOpcode(); in mergeSPUpdatesUp() local
239 unsigned Opc = NI->getOpcode(); in mergeSPUpdatesDown() local
271 unsigned Opc = PI->getOpcode(); in mergeSPUpdates() local
526 unsigned Opc = MI.getOpcode(); in getCompactUnwindEncoding() local
952 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr; in emitPrologue() local
1062 unsigned Opc = PI->getOpcode(); in emitEpilogue() local
1086 unsigned Opc = getLEArOpcode(IsLP64); in emitEpilogue() local
1090 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); in emitEpilogue() local
[all …]
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| D | X86FastISel.cpp | 183 unsigned Opc = 0; in X86FastEmitLoad() local
241 unsigned Opc = 0; in X86FastEmitStore() local
292 unsigned Opc = 0; in X86FastEmitStore() local
326 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
541 unsigned Opc = 0; in X86SelectAddress() local
1244 unsigned Opc = 0; in X86SelectSelect() local
1514 unsigned Opc = X86::SETBr; in X86VisitIntrinsicCall() local
2040 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in DoSelectCall() local
2121 unsigned Opc = 0; in TargetMaterializeConstant() local
2229 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; in TargetMaterializeAlloca() local
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| D | X86ISelDAGToDAG.cpp | 1491 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { in SelectAtomic64()
1726 unsigned Opc = 0; in SelectAtomicLoadArith() local
1850 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc, in isLoadIncOrDecStore()
1935 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) { in getFusedLdStOpcode()
1953 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) { in SelectGather()
1985 unsigned Opc, MOpc; in Select() local
2018 unsigned Opc; in Select() local
2062 unsigned Opc; in Select() local
2654 unsigned Opc = StoredVal->getOpcode(); in Select() local
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode(); in isIntS32Immediate() local
213 unsigned Opc = MBlaze::ADDIK; in Select() local
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| D | MBlazeInstrInfo.h | 144 inline static bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
155 inline static bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch() local
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch() local
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| /external/llvm/lib/MC/ |
| D | MCExpr.cpp | 151 const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS, in Create()
156 const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr, in Create()
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