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Searched defs:RC (Results 1 – 25 of 119) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h69 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
85 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
92 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
102 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
118 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
126 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/llvm/include/llvm/IR/
DIRBuilder.h573 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
587 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
595 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
609 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
617 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
631 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
639 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
651 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
663 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
670 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp36 const TargetRegisterClass *RC; in getGlobalBaseReg() local
54 const TargetRegisterClass *RC; in getMips16SPAliasReg() local
62 const TargetRegisterClass *RC = ST.isABI_N64() ? in createEhDataRegsFI() local
DMipsSEFrameLowering.cpp121 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue() local
187 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitEpilogue() local
235 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
294 const TargetRegisterClass *RC = STI.isABI_N64() ? in processFunctionBeforeCalleeSavedScan() local
DMipsSEInstrInfo.cpp157 const TargetRegisterClass *RC, in storeRegToStackSlot()
184 const TargetRegisterClass *RC, in loadRegFromStackSlot()
284 const TargetRegisterClass *RC = STI.isABI_N64() ? in loadImmediate() local
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h125 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
144 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
431 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
457 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg()
557 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
566 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
578 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
633 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { in avoidWriteAfterWrite()
[all …]
/external/llvm/lib/CodeGen/
DLiveStackAnalysis.cpp58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
80 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
DPrologEpilogInserter.cpp236 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters() local
304 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
331 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
379 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
430 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
846 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg); in scavengeFrameVirtualRegs() local
DTargetRegisterInfo.cpp108 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
121 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
225 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
DAggressiveAntiDepBreaker.h45 const TargetRegisterClass *RC; member
DVirtRegMap.cpp73 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { in createSpillSlot()
102 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot() local
DRegisterScavenging.cpp239 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable()
329 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, in scavengeRegister()
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) { in getNVPTXRegClassName()
63 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp54 const TargetRegisterClass *RC, in storeRegToStackSlot()
82 const TargetRegisterClass *RC, in loadRegFromStackSlot()
DARMFastISel.cpp294 const TargetRegisterClass* RC) { in FastEmitInst_()
303 const TargetRegisterClass *RC, in FastEmitInst_r()
322 const TargetRegisterClass *RC, in FastEmitInst_rr()
344 const TargetRegisterClass *RC, in FastEmitInst_rrr()
369 const TargetRegisterClass *RC, in FastEmitInst_ri()
391 const TargetRegisterClass *RC, in FastEmitInst_rf()
413 const TargetRegisterClass *RC, in FastEmitInst_rri()
438 const TargetRegisterClass *RC, in FastEmitInst_i()
457 const TargetRegisterClass *RC, in FastEmitInst_ii()
568 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1192 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { in createResultReg()
1197 const TargetRegisterClass* RC) { in FastEmitInst_()
1206 const TargetRegisterClass *RC, in FastEmitInst_r()
1225 const TargetRegisterClass *RC, in FastEmitInst_rr()
1246 const TargetRegisterClass *RC, in FastEmitInst_rrr()
1270 const TargetRegisterClass *RC, in FastEmitInst_ri()
1291 const TargetRegisterClass *RC, in FastEmitInst_rii()
1314 const TargetRegisterClass *RC, in FastEmitInst_rf()
1335 const TargetRegisterClass *RC, in FastEmitInst_rri()
1359 const TargetRegisterClass *RC, in FastEmitInst_rrii()
[all …]
DResourcePriorityQueue.cpp370 const TargetRegisterClass *RC = *I; in regPressureDelta() local
377 const TargetRegisterClass *RC = *I; in regPressureDelta() local
491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
502 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp172 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; in EmitRegUnitPressure() local
846 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
880 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
988 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetHeader() local
1026 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1091 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1120 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1136 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
1172 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
1238 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; in runTargetDesc() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp441 const TargetRegisterClass *RC, in StoreRegToStackSlot()
544 const TargetRegisterClass *RC, in storeRegToStackSlot()
574 const TargetRegisterClass *RC, in LoadRegFromStackSlot()
652 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp37 const TargetRegisterClass *RC, in storeRegToStackSlot()
65 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.cpp95 const TargetRegisterClass *RC, in storeRegToStackSlot()
105 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp300 const TargetRegisterClass *RC, in storeRegToStackSlot()
322 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/clang/test/CodeGenCXX/
Ddevirtualize-virtual-function-calls-final.cpp169 struct RC final : public RA { struct
170 virtual C *f() { in f()
/external/llvm/lib/Target/XCore/
DXCoreFrameLowering.cpp292 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
318 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters() local
393 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in processFunctionBeforeCalleeSavedScan() local
DXCoreInstrInfo.cpp365 const TargetRegisterClass *RC, in storeRegToStackSlot()
379 const TargetRegisterClass *RC, in loadRegFromStackSlot()

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