1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "nvptx-reg-info"
15
16 #include "NVPTXRegisterInfo.h"
17 #include "NVPTX.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25
26
27 using namespace llvm;
28
29 namespace llvm
30 {
getNVPTXRegClassName(TargetRegisterClass const * RC)31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
32 if (RC == &NVPTX::Float32RegsRegClass) {
33 return ".f32";
34 }
35 if (RC == &NVPTX::Float64RegsRegClass) {
36 return ".f64";
37 }
38 else if (RC == &NVPTX::Int64RegsRegClass) {
39 return ".s64";
40 }
41 else if (RC == &NVPTX::Int32RegsRegClass) {
42 return ".s32";
43 }
44 else if (RC == &NVPTX::Int16RegsRegClass) {
45 return ".s16";
46 }
47 // Int8Regs become 16-bit registers in PTX
48 else if (RC == &NVPTX::Int8RegsRegClass) {
49 return ".s16";
50 }
51 else if (RC == &NVPTX::Int1RegsRegClass) {
52 return ".pred";
53 }
54 else if (RC == &NVPTX::SpecialRegsRegClass) {
55 return "!Special!";
56 }
57 else {
58 return "INTERNAL";
59 }
60 return "";
61 }
62
getNVPTXRegClassStr(TargetRegisterClass const * RC)63 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
64 if (RC == &NVPTX::Float32RegsRegClass) {
65 return "%f";
66 }
67 if (RC == &NVPTX::Float64RegsRegClass) {
68 return "%fd";
69 }
70 else if (RC == &NVPTX::Int64RegsRegClass) {
71 return "%rd";
72 }
73 else if (RC == &NVPTX::Int32RegsRegClass) {
74 return "%r";
75 }
76 else if (RC == &NVPTX::Int16RegsRegClass) {
77 return "%rs";
78 }
79 else if (RC == &NVPTX::Int8RegsRegClass) {
80 return "%rc";
81 }
82 else if (RC == &NVPTX::Int1RegsRegClass) {
83 return "%p";
84 }
85 else if (RC == &NVPTX::SpecialRegsRegClass) {
86 return "!Special!";
87 }
88 else {
89 return "INTERNAL";
90 }
91 return "";
92 }
93 }
94
NVPTXRegisterInfo(const TargetInstrInfo & tii,const NVPTXSubtarget & st)95 NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
96 const NVPTXSubtarget &st)
97 : NVPTXGenRegisterInfo(0),
98 Is64Bit(st.is64Bit()) {}
99
100 #define GET_REGINFO_TARGET_DESC
101 #include "NVPTXGenRegisterInfo.inc"
102
103 /// NVPTX Callee Saved Registers
104 const uint16_t* NVPTXRegisterInfo::
getCalleeSavedRegs(const MachineFunction * MF) const105 getCalleeSavedRegs(const MachineFunction *MF) const {
106 static const uint16_t CalleeSavedRegs[] = { 0 };
107 return CalleeSavedRegs;
108 }
109
110 // NVPTX Callee Saved Reg Classes
111 const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction * MF) const112 NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
113 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
114 return CalleeSavedRegClasses;
115 }
116
getReservedRegs(const MachineFunction & MF) const117 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
118 BitVector Reserved(getNumRegs());
119 return Reserved;
120 }
121
122 void NVPTXRegisterInfo::
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const123 eliminateFrameIndex(MachineBasicBlock::iterator II,
124 int SPAdj, unsigned FIOperandNum,
125 RegScavenger *RS) const {
126 assert(SPAdj == 0 && "Unexpected");
127
128 MachineInstr &MI = *II;
129 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
130
131 MachineFunction &MF = *MI.getParent()->getParent();
132 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
133 MI.getOperand(FIOperandNum+1).getImm();
134
135 // Using I0 as the frame pointer
136 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
137 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
138 }
139
140 int NVPTXRegisterInfo::
getDwarfRegNum(unsigned RegNum,bool isEH) const141 getDwarfRegNum(unsigned RegNum, bool isEH) const {
142 return 0;
143 }
144
getFrameRegister(const MachineFunction & MF) const145 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
146 return NVPTX::VRFrame;
147 }
148
getRARegister() const149 unsigned NVPTXRegisterInfo::getRARegister() const {
150 return 0;
151 }
152
153