| /external/llvm/lib/Transforms/Scalar/ |
| D | CodeGenPrepare.cpp | 826 struct ExtAddrMode : public TargetLowering::AddrMode {
896 ExtAddrMode &AddrMode; member in __anon3005b4ff0311::AddressingModeMatcher
906 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) { in AddressingModeMatcher()
952 if (AddrMode.Scale != 0 && AddrMode.ScaledReg != ScaleReg) in MatchScaledValue()
955 ExtAddrMode TestAddrMode = AddrMode; in MatchScaledValue()
967 AddrMode = TestAddrMode; in MatchScaledValue()
982 AddrMode = TestAddrMode; in MatchScaledValue()
1052 ExtAddrMode BackupAddrMode = AddrMode; in MatchOperationAddr()
1059 AddrMode = BackupAddrMode; in MatchOperationAddr()
1068 AddrMode = BackupAddrMode; in MatchOperationAddr()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 393 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in rewriteT2FrameIndex() local
398 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? in rewriteT2FrameIndex()
468 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) in rewriteT2FrameIndex()
474 if (AddrMode == ARMII::AddrModeT2_so) { in rewriteT2FrameIndex()
484 AddrMode = ARMII::AddrModeT2_i12; in rewriteT2FrameIndex()
489 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) { in rewriteT2FrameIndex()
503 } else if (AddrMode == ARMII::AddrMode5) { in rewriteT2FrameIndex()
534 if (AddrMode == ARMII::AddrMode5) in rewriteT2FrameIndex()
548 if (AddrMode == ARMII::AddrMode5) in rewriteT2FrameIndex()
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| D | ARMInstrFormats.td | 90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
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| D | ARMBaseRegisterInfo.cpp | 407 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in getFrameIndexInstrOffset() local
411 switch (AddrMode) { in getFrameIndexInstrOffset()
596 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in isFrameOffsetLegal() local
605 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) in isFrameOffsetLegal()
611 switch (AddrMode) { in isFrameOffsetLegal()
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| D | ARMISelLowering.h | 303 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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| D | Thumb1RegisterInfo.cpp | 355 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in rewriteFrameIndex() local
439 if (AddrMode != ARMII::AddrModeT1_s) in rewriteFrameIndex()
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| D | ARMBaseInstrInfo.cpp | 151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in convertToThreeAddress() local
163 switch (AddrMode) { in convertToThreeAddress()
1807 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in rewriteARMFrameIndex() local
1812 AddrMode = ARMII::AddrMode2; in rewriteARMFrameIndex()
1855 switch (AddrMode) { in rewriteARMFrameIndex()
1915 if (AddrMode == ARMII::AddrMode_i12) in rewriteARMFrameIndex()
1928 if (AddrMode == ARMII::AddrMode_i12) in rewriteARMFrameIndex()
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| D | ARMInstrThumb.td | 555 AddrMode am, InstrItinClass itin_r,
572 AddrMode am, InstrItinClass itin_r,
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 191 enum AddrMode { enum
211 inline static const char *AddrModeToString(AddrMode addrmode) { in AddrModeToString()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 62 enum AddrMode { enum
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.h | 98 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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| D | NVPTXISelLowering.cpp | 1329 NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| /external/v8/src/arm/ |
| D | assembler-arm.h | 459 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
464 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
470 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
484 AddrMode am() const { return am_; } in am()
496 AddrMode am_; // bits P, U, and W
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| D | constants-arm.h | 318 enum AddrMode { enum
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| D | assembler-arm.cc | 208 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) { in MemOperand()
215 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { in MemOperand()
225 ShiftOp shift_op, int shift_imm, AddrMode am) { in MemOperand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 162 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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| D | HexagonISelLowering.cpp | 1608 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.h | 106 virtual bool isLegalAddressingMode(const AddrMode &AM,
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| D | XCoreISelLowering.cpp | 1588 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1136 struct AddrMode { struct
1141 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode() argument
1149 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 420 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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| /external/llvm/lib/CodeGen/ |
| D | BasicTargetTransformInfo.cpp | 132 TargetLoweringBase::AddrMode AM; in isLegalAddressingMode()
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| D | TargetLoweringBase.cpp | 1276 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, in isLegalAddressingMode()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 423 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 610 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|