1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef Hexagon_ISELLOWERING_H 16 #define Hexagon_ISELLOWERING_H 17 18 #include "Hexagon.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/IR/CallingConv.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace HexagonISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 CONST32, 29 CONST32_GP, // For marking data present in GP. 30 CONST32_Int_Real, 31 FCONST32, 32 SETCC, 33 ADJDYNALLOC, 34 ARGEXTEND, 35 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 SELECT_ICC, // Select between two values using the current ICC flags. 41 SELECT_FCC, // Select between two values using the current FCC flags. 42 43 Hi, Lo, // Hi/Lo operations, typically on a global address. 44 45 FTOI, // FP to Int within a FP register. 46 ITOF, // Int to FP within a FP register. 47 48 CALL, // A call instruction. 49 RET_FLAG, // Return with a flag operand. 50 BR_JT, // Jump table. 51 BARRIER, // Memory barrier. 52 WrapperJT, 53 WrapperCP, 54 WrapperCombineII, 55 WrapperCombineRR, 56 WrapperCombineRI_V4, 57 WrapperCombineIR_V4, 58 WrapperPackhl, 59 WrapperSplatB, 60 WrapperSplatH, 61 WrapperShuffEB, 62 WrapperShuffEH, 63 WrapperShuffOB, 64 WrapperShuffOH, 65 TC_RETURN 66 }; 67 } 68 69 class HexagonTargetLowering : public TargetLowering { 70 int VarArgsFrameOffset; // Frame offset to start of varargs area. 71 72 bool CanReturnSmallStruct(const Function* CalleeFn, 73 unsigned& RetSize) const; 74 75 public: 76 HexagonTargetMachine &TM; 77 explicit HexagonTargetLowering(HexagonTargetMachine &targetmachine); 78 79 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 80 /// for tail call optimization. Targets which want to do tail call 81 /// optimization should implement this function. 82 bool 83 IsEligibleForTailCallOptimization(SDValue Callee, 84 CallingConv::ID CalleeCC, 85 bool isVarArg, 86 bool isCalleeStructRet, 87 bool isCallerStructRet, 88 const 89 SmallVectorImpl<ISD::OutputArg> &Outs, 90 const SmallVectorImpl<SDValue> &OutVals, 91 const SmallVectorImpl<ISD::InputArg> &Ins, 92 SelectionDAG& DAG) const; 93 94 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 95 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 96 97 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 98 99 virtual const char *getTargetNodeName(unsigned Opcode) const; 100 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 102 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; 104 SDValue LowerFormalArguments(SDValue Chain, 105 CallingConv::ID CallConv, bool isVarArg, 106 const SmallVectorImpl<ISD::InputArg> &Ins, 107 DebugLoc dl, SelectionDAG &DAG, 108 SmallVectorImpl<SDValue> &InVals) const; 109 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 111 112 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 113 SmallVectorImpl<SDValue> &InVals) const; 114 115 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 116 CallingConv::ID CallConv, bool isVarArg, 117 const SmallVectorImpl<ISD::InputArg> &Ins, 118 DebugLoc dl, SelectionDAG &DAG, 119 SmallVectorImpl<SDValue> &InVals, 120 const SmallVectorImpl<SDValue> &OutVals, 121 SDValue Callee) const; 122 123 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 124 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 125 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 126 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 127 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 128 129 SDValue LowerReturn(SDValue Chain, 130 CallingConv::ID CallConv, bool isVarArg, 131 const SmallVectorImpl<ISD::OutputArg> &Outs, 132 const SmallVectorImpl<SDValue> &OutVals, 133 DebugLoc dl, SelectionDAG &DAG) const; 134 135 virtual MachineBasicBlock 136 *EmitInstrWithCustomInserter(MachineInstr *MI, 137 MachineBasicBlock *BB) const; 138 139 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; getSetCCResultType(EVT VT)141 virtual EVT getSetCCResultType(EVT VT) const { 142 return MVT::i1; 143 } 144 145 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 146 SDValue &Base, SDValue &Offset, 147 ISD::MemIndexedMode &AM, 148 SelectionDAG &DAG) const; 149 150 std::pair<unsigned, const TargetRegisterClass*> 151 getRegForInlineAsmConstraint(const std::string &Constraint, 152 EVT VT) const; 153 154 // Intrinsics 155 virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, 156 SelectionDAG &DAG) const; 157 /// isLegalAddressingMode - Return true if the addressing mode represented 158 /// by AM is legal for this target, for a load/store of the specified type. 159 /// The type may be VoidTy, in which case only return true if the addressing 160 /// mode is legal for a load/store of any legal type. 161 /// TODO: Handle pre/postinc as well. 162 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 163 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 164 165 /// isLegalICmpImmediate - Return true if the specified immediate is legal 166 /// icmp immediate, that is the target has icmp instructions which can 167 /// compare a register against the immediate without having to materialize 168 /// the immediate into a register. 169 virtual bool isLegalICmpImmediate(int64_t Imm) const; 170 }; 171 } // end namespace llvm 172 173 #endif // Hexagon_ISELLOWERING_H 174