| /external/valgrind/main/cachegrind/ |
| D | cg-x86-amd64.c | 62 Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* LLc) in Intel_cache_info() argument
126 case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break; in Intel_cache_info()
127 case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break; in Intel_cache_info()
128 case 0x0d: *D1c = (cache_t) { 16, 4, 64 }; break; in Intel_cache_info()
129 case 0x0e: *D1c = (cache_t) { 24, 6, 64 }; break; in Intel_cache_info()
130 case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break; in Intel_cache_info()
196 case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */ in Intel_cache_info()
197 case 0x66: *D1c = (cache_t) { 8, 4, 64 }; break; /* sectored */ in Intel_cache_info()
198 case 0x67: *D1c = (cache_t) { 16, 4, 64 }; break; /* sectored */ in Intel_cache_info()
199 case 0x68: *D1c = (cache_t) { 32, 4, 64 }; break; /* sectored */ in Intel_cache_info()
[all …]
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| D | cg-arch.c | 161 cache_t* D1c, in VG_()
177 VG_(configure_caches)( I1c, D1c, LLc, all_caches_clo_defined ); in VG_()
183 check_cache_or_override ("D1", D1c, DEFINED(clo_D1c)); in VG_()
189 if (DEFINED(clo_D1c)) { *D1c = *clo_D1c; } in VG_()
195 umsg_cache_img ("D1", D1c); in VG_()
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| D | cg-s390x.c | 42 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, in VG_()
107 *D1c = (cache_t) { 131072, 8, 256 }; in VG_()
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| D | cg-ppc64.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, in VG_()
45 *D1c = (cache_t) { 65536, 2, 64 }; in VG_()
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| D | cg-ppc32.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, in VG_()
45 *D1c = (cache_t) { 65536, 2, 64 }; in VG_()
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| D | cg-mips32.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, in VG_()
45 *D1c = (cache_t) { 32768, 4, 32 }; in VG_()
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| D | cg-arm.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, in VG_()
45 *D1c = (cache_t) { 16384, 4, 64 }; in VG_()
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| D | cg_arch.h | 49 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
67 cache_t* D1c,
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| D | cg_main.c | 1710 cache_t I1c, D1c, LLc; in cg_post_clo_init() local
1728 VG_(post_clo_init_configure_caches)(&I1c, &D1c, &LLc, in cg_post_clo_init()
1736 min_line_size = (I1c.line_size < D1c.line_size) ? I1c.line_size : D1c.line_size; in cg_post_clo_init()
1754 cachesim_D1_initcache(D1c); in cg_post_clo_init()
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| /external/valgrind/main/callgrind/ |
| D | sim.c | 1277 cache_t I1c, D1c, LLc; in cachesim_post_clo_init() local
1301 VG_(post_clo_init_configure_caches)(&I1c, &D1c, &LLc, in cachesim_post_clo_init()
1313 CLG_(min_line_size) = (I1c.line_size < D1c.line_size) in cachesim_post_clo_init()
1314 ? I1c.line_size : D1c.line_size; in cachesim_post_clo_init()
1333 cachesim_initcache(D1c, &D1); in cachesim_post_clo_init()
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| /external/valgrind/main/docs/internals/ |
| D | porting-to-ARM.txt | 51 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
59 *D1c = (cache_t) { 4096, 2, 32 };
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