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Searched refs:ImplicitDefine (Results 1 – 9 of 9) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h40 ImplicitDefine = Implicit | Define, enumerator
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
965 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
DARMFrameLowering.cpp927 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
942 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
DARMBaseInstrInfo.cpp985 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1018 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1039 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1059 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
DARMLoadStoreOptimizer.cpp358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); in MergeOps()
DARMISelLowering.cpp6675 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
/external/llvm/lib/CodeGen/
DPostRASchedulerList.cpp457 MIB.addReg(*SubRegs, RegState::ImplicitDefine); in ToggleKillFlag()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp14076 .addReg(X86::RAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
14084 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
14197 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
14208 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
14219 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
DX86InstrInfo.cpp3852 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()