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Searched refs:MCID (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrDesc.h98 namespace MCID {
191 return Flags & (1 << MCID::Variadic); in isVariadic()
197 return Flags & (1 << MCID::HasOptionalDef); in hasOptionalDef()
204 return Flags & (1 << MCID::Pseudo); in isPseudo()
209 return Flags & (1 << MCID::Return); in isReturn()
214 return Flags & (1 << MCID::Call); in isCall()
221 return Flags & (1 << MCID::Barrier); in isBarrier()
231 return Flags & (1 << MCID::Terminator); in isTerminator()
239 return Flags & (1 << MCID::Branch); in isBranch()
245 return Flags & (1 << MCID::IndirectBranch); in isIndirectBranch()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInst.cpp33 const uint64_t F = MCID->TSFlags; in getType()
40 return (!MCID->isPseudo() && in isCanon()
52 const uint64_t F = MCID->TSFlags; in isSolo()
58 const uint64_t F = MCID->TSFlags; in isNewValue()
64 const uint64_t F = MCID->TSFlags; in hasNewValue()
70 const uint64_t F = MCID->TSFlags; in getNewValue()
118 const uint64_t F = MCID->TSFlags; in isExtended()
124 const uint64_t F = MCID->TSFlags; in isExtendable()
130 const uint64_t F = MCID->TSFlags; in getBitCount()
136 const uint64_t F = MCID->TSFlags; in getCExtOpNum()
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DHexagonMCInst.h27 const MCInstrDesc *MCID; variable
34 MCInst(), MCID(0), packetStart(0), packetEnd(0) {}; in HexagonMCInst()
36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {}; in HexagonMCInst()
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; }; in setDesc()
51 const MCInstrDesc& getDesc(void) const { return *MCID; }; in getDesc()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h70 const MCInstrDesc *MCID; // Instruction descriptor.
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
257 const MCInstrDesc &getDesc() const { return *MCID; }
261 int getOpcode() const { return MCID->Opcode; }
329 return hasProperty(MCID::Variadic, Type);
335 return hasProperty(MCID::HasOptionalDef, Type);
342 return hasProperty(MCID::Pseudo, Type);
346 return hasProperty(MCID::Return, Type);
350 return hasProperty(MCID::Call, Type);
357 return hasProperty(MCID::Barrier, Type);
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DMachineInstrBuilder.h225 const MCInstrDesc &MCID) { in BuildMI() argument
226 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); in BuildMI()
234 const MCInstrDesc &MCID, in BuildMI() argument
236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) in BuildMI()
247 const MCInstrDesc &MCID, in BuildMI() argument
250 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
258 const MCInstrDesc &MCID, in BuildMI() argument
261 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
269 const MCInstrDesc &MCID, in BuildMI() argument
273 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
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/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue() local
282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? in getHiLo16ImmOpValue()
485 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue() local
487 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) in getMachineOpValue()
821 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction() local
829 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelInstruction()
848 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction() local
857 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelJTInstruction()
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DThumb2SizeReduction.cpp203 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef() argument
204 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
523 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
524 if (MCID.hasOptionalDef() && in ReduceSpecial()
525 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
673 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
674 if (MCID.hasOptionalDef()) { in ReduceTo2Addr()
675 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
701 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
703 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
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DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
26 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
DMLxExpansionPass.cpp186 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
187 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
190 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
343 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
351 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
361 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
DThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate() local
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) in emitThumbRegPlusImmediate()
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate() local
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) in emitThumbRegPlusImmediate()
319 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant() local
320 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) in emitThumbConstant()
DThumb2ITBlockPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
DARMBaseRegisterInfo.cpp553 const MCInstrDesc &MCID = TII.get(ADDriOpc); in materializeFrameBaseRegister() local
556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
129 if (MCID == NULL) { in getHazardType()
133 unsigned idx = MCID->getSchedClass(); in getHazardType()
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
185 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction()
186 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction()
193 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
DTargetInstrInfo.cpp39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() argument
42 if (OpNum >= MCID.getNumOperands()) in getRegClass()
45 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass()
46 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass()
120 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
121 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
185 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
186 if (!MCID.isCommutable()) in findCommutedOpIndices()
190 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
220 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
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DMachineInstr.cpp521 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()
524 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
525 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) in addImplicitDefUseOperands()
534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0), in MachineInstr()
538 if (unsigned NumOps = MCID->getNumOperands() + in MachineInstr()
539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { in MachineInstr()
551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0), in MachineInstr()
623 assert(MCID && "Cannot add operands before providing an instr descriptor"); in addOperand()
653 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || in addOperand()
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DMachineVerifier.cpp760 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
761 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
763 *OS << MCID.getNumOperands() << " operands expected, but " in visitMachineInstrBefore()
804 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local
807 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
808 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
815 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
816 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
820 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { in visitMachineOperand()
827 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
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DPeepholeOptimizer.cpp421 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable() local
422 if (MCID.getNumDefs() != 1) in isLoadFoldable()
441 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
444 if (MCID.getNumDefs() != 1) in isMoveImmediate()
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
28 if (!MCID) in EmitInstruction()
94 const MCInstrDesc &MCID = TII.get(Opcode); in GetInstrType() local
96 isLoad = MCID.mayLoad(); in GetInstrType()
97 isStore = MCID.mayStore(); in GetInstrType()
99 uint64_t TSFlags = MCID.TSFlags; in GetInstrType()
DPPCInstrInfo.cpp428 const MCInstrDesc &MCID = get(Opc); in copyPhysReg() local
429 if (MCID.getNumOperands() == 3) in copyPhysReg()
430 BuildMI(MBB, I, DL, MCID, DestReg) in copyPhysReg()
433 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
258 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
264 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
436 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
437 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
438 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
514 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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DInstrEmitter.cpp308 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() local
309 bool isOptDef = IIOpNum < MCID.getNumOperands() && in AddRegisterOperand()
310 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
345 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
802 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
803 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
804 MCID.getImplicitUses() + MCID.getNumImplicitUses()); in EmitMachineNode()
DScheduleDAGRRList.cpp1002 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
1003 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
1004 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
1009 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
1192 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1193 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1194 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1195 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1318 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
1319 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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DScheduleDAGSDNodes.cpp299 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
300 if (MCID.mayLoad()) in ClusterNodes()
434 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in AddSchedEdges()
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
441 if (MCID.isCommutable()) in AddSchedEdges()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h152 const MCInstrDesc &MCID = MI->getDesc(); variable
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp108 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr()

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