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Searched refs:MI (Results 1 – 25 of 441) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp29 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, in EmitAnyX86InstComments() argument
35 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
38 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
39 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
40 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
41 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
46 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
47 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
48 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
54 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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DX86ATTInstPrinter.h30 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
37 void printInstruction(const MCInst *MI, raw_ostream &OS);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
41 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
42 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printopaquemem() argument
47 printMemReference(MI, OpNo, O); in printopaquemem()
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DX86IntelInstPrinter.h31 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
41 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printopaquemem() argument
45 printMemReference(MI, OpNo, O); in printopaquemem()
48 void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printi8mem() argument
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h29 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
33 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
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DARMInstPrinter.cpp75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
77 unsigned Opcode = MI->getOpcode(); in printInst()
81 switch (MI->getOperand(0).getImm()) { in printInst()
89 printInstruction(MI, O); in printInst()
93 printPredicateOperand(MI, 1, O); in printInst()
103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst()
106 const MCOperand &MO3 = MI->getOperand(3); in printInst()
109 printSBitModifierOperand(MI, 6, O); in printInst()
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/external/llvm/lib/Target/R600/
DSILowerControlFlow.cpp75 void SkipIfDead(MachineInstr &MI);
77 void If(MachineInstr &MI);
78 void Else(MachineInstr &MI);
79 void Break(MachineInstr &MI);
80 void IfBreak(MachineInstr &MI);
81 void ElseBreak(MachineInstr &MI);
82 void Loop(MachineInstr &MI);
83 void EndCf(MachineInstr &MI);
85 void Kill(MachineInstr &MI);
86 void Branch(MachineInstr &MI);
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/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp49 bool LowerSubregToReg(MachineInstr *MI);
50 bool LowerCopy(MachineInstr *MI);
52 void TransferImplicitDefs(MachineInstr *MI);
66 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
67 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
70 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
71 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
78 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
79 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
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DTargetInstrInfo.cpp60 MachineBasicBlock::iterator MI) const { in insertNoop()
118 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI, in commuteInstruction() argument
120 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
122 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction()
126 if (!findCommutedOpIndices(MI, Idx1, Idx2)) { in commuteInstruction()
129 Msg << "Don't know how to commute: " << *MI; in commuteInstruction()
133 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction()
135 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction()
136 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction()
137 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction()
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/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
92 void emitConstPoolInstruction(const MachineInstr &MI);
93 void emitMOVi32immInstruction(const MachineInstr &MI);
94 void emitMOVi2piecesInstruction(const MachineInstr &MI);
95 void emitLEApcrelInstruction(const MachineInstr &MI);
96 void emitLEApcrelJTInstruction(const MachineInstr &MI);
97 void emitPseudoMoveInstruction(const MachineInstr &MI);
99 void emitPseudoInstruction(const MachineInstr &MI);
100 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
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DA15SDOptimizer.cpp65 bool runOnInstruction(MachineInstr *MI);
105 bool hasPartialWrite(MachineInstr *MI);
106 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
113 MachineInstr *elideCopies(MachineInstr *MI);
114 void elideCopiesAndPHIs(MachineInstr *MI,
120 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
121 unsigned optimizeSDPattern(MachineInstr *MI);
127 void eraseInstrWithNoUses(MachineInstr *MI);
164 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane() local
165 if (!MI) return ARM::ssub_0; in getPrefSPRLane()
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DThumb2SizeReduction.cpp155 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
159 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
162 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
168 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
175 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
181 bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
264 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, in VerifyPredAndCC() argument
294 if (!HasImplicitCPSRDef(MI->getDesc())) in VerifyPredAndCC()
306 static bool VerifyLowRegs(MachineInstr *MI) { in VerifyLowRegs() argument
307 unsigned Opc = MI->getOpcode(); in VerifyLowRegs()
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DMLxExpansionPass.cpp61 void pushStack(MachineInstr *MI);
62 MachineInstr *getAccDefMI(MachineInstr *MI) const;
63 unsigned getDefReg(MachineInstr *MI) const;
64 bool hasLoopHazard(MachineInstr *MI) const;
65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
66 bool FindMLxHazard(MachineInstr *MI);
67 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
80 void MLxExpansion::pushStack(MachineInstr *MI) { in pushStack() argument
81 LastMIs[MIIdx] = MI; in pushStack()
86 MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const { in getAccDefMI()
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp30 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
33 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
34 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
35 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
36 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
46 printOperand(MI, 0, O); in printInst()
48 printOperand(MI, 1, O); in printInst()
56 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
59 printOperand(MI, 0, O); in printInst()
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitTFRCondSets.cpp84 MachineInstr *MI = MII; in runOnMachineFunction() local
86 switch(MI->getOpcode()) { in runOnMachineFunction()
90 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
91 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
92 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction()
94 if (MI->getOpcode() == Hexagon::TFR_condset_rr || in runOnMachineFunction()
95 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { in runOnMachineFunction()
99 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { in runOnMachineFunction()
107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1), in runOnMachineFunction()
108 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
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DHexagonRegisterInfo.cpp127 MachineInstr &MI = *II; in eliminateFrameIndex() local
128 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); in eliminateFrameIndex()
131 MachineFunction &MF = *MI.getParent()->getParent(); in eliminateFrameIndex()
145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
146 !TII.isSpillPredRegOp(&MI)) { in eliminateFrameIndex()
148 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false, in eliminateFrameIndex()
150 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset); in eliminateFrameIndex()
153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { in eliminateFrameIndex()
162 if ( (MI.getOpcode() == Hexagon::LDriw) || in eliminateFrameIndex()
163 (MI.getOpcode() == Hexagon::LDrid) || in eliminateFrameIndex()
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DHexagonAsmPrinter.h39 virtual void EmitInstruction(const MachineInstr *MI);
43 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
44 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
47 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
55 void printInstruction(const MachineInstr *MI, raw_ostream &O);
69 void printImmOperand(const MachineInstr *MI, unsigned OpNo, in printImmOperand() argument
71 int value = MI->getOperand(OpNo).getImm(); in printImmOperand()
75 void printNegImmOperand(const MachineInstr *MI, unsigned OpNo, in printNegImmOperand() argument
77 int value = MI->getOperand(OpNo).getImm(); in printNegImmOperand()
81 void printMEMriOperand(const MachineInstr *MI, unsigned OpNo, in printMEMriOperand() argument
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/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h32 void printInstruction(const MCInst *MI, raw_ostream &O);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
40 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum, in printAddrRegExtendOperand() argument
42 printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize); in printAddrRegExtendOperand()
46 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
50 void printAddSubImmLSL0Operand(const MCInst *MI,
52 void printAddSubImmLSL12Operand(const MCInst *MI,
55 void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
58 void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
59 void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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DAArch64InstPrinter.cpp53 AArch64InstPrinter::printOffsetSImm9Operand(const MCInst *MI, in printOffsetSImm9Operand() argument
55 const MCOperand &MOImm = MI->getOperand(OpNum); in printOffsetSImm9Operand()
62 AArch64InstPrinter::printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum, in printAddrRegExtendOperand() argument
65 unsigned ExtImm = MI->getOperand(OpNum).getImm(); in printAddrRegExtendOperand()
92 AArch64InstPrinter::printAddSubImmLSL0Operand(const MCInst *MI, in printAddSubImmLSL0Operand() argument
94 const MCOperand &Imm12Op = MI->getOperand(OpNum); in printAddSubImmLSL0Operand()
107 AArch64InstPrinter::printAddSubImmLSL12Operand(const MCInst *MI, unsigned OpNum, in printAddSubImmLSL12Operand() argument
110 printAddSubImmLSL0Operand(MI, OpNum, O); in printAddSubImmLSL12Operand()
116 AArch64InstPrinter::printBareImmOperand(const MCInst *MI, unsigned OpNum, in printBareImmOperand() argument
118 const MCOperand &MO = MI->getOperand(OpNum); in printBareImmOperand()
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/external/llvm/lib/Target/Hexagon/InstPrinter/
DHexagonInstPrinter.cpp41 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
43 printInst((const HexagonMCInst*)(MI), O, Annot); in printInst()
46 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O, in printInst() argument
51 if (MI->getOpcode() == Hexagon::ENDLOOP0) { in printInst()
53 assert(MI->isPacketEnd() && "Loop-end must also end the packet"); in printInst()
55 if (MI->isPacketStart()) { in printInst()
62 Nop.setPacketStart (MI->isPacketStart()); in printInst()
67 if (MI->isPacketEnd()) in printInst()
70 printInstruction(MI, O); in printInst()
74 if (MI->isPacketStart()) in printInst()
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp69 uint64_t getBinaryCodeForInstr(const MCInst &MI,
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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/external/llvm/lib/Target/PowerPC/
DPPCCodeEmitter.cpp53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
60 unsigned getMachineOpValue(const MachineInstr &MI,
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
67 unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
68 unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
69 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
71 unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
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/external/llvm/lib/Target/Mips/
DMipsCodeEmitter.cpp82 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
84 void emitInstruction(MachineBasicBlock::instr_iterator MI,
102 unsigned getMachineOpValue(const MachineInstr &MI,
105 unsigned getRelocation(const MachineInstr &MI,
108 unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
110 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
111 unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
112 unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
113 unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
119 bool expandPseudos(MachineBasicBlock::instr_iterator &MI,
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp54 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
56 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
58 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
60 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
62 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
64 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
66 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
68 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
73 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
78 uint64_t getBinaryCodeForInstr(const MCInst &MI,
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/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp40 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
41 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
43 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
45 virtual void EmitInstruction(const MachineInstr *MI) { in EmitInstruction() argument
48 printInstruction(MI, OS); in EmitInstruction()
51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
54 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
57 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
61 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
66 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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/external/llvm/lib/Target/R600/InstPrinter/
DAMDGPUInstPrinter.cpp18 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
20 printInstruction(MI, OS); in printInst()
25 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
28 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
47 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, in printInterpSlot() argument
49 unsigned Imm = MI->getOperand(OpNum).getImm(); in printInterpSlot()
62 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, in printMemOperand() argument
64 printOperand(MI, OpNo, O); in printMemOperand()
66 printOperand(MI, OpNo + 1, O); in printMemOperand()
69 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo, in printIfSet() argument
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