/external/llvm/lib/Target/X86/ |
D | X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem() 98 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument 99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset() 107 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset() 114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument 117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg() 122 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument 127 MIB.addReg(AM.Base.Reg); in addFullAddress() [all …]
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D | X86InstrInfo.cpp | 1809 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), in convertToThreeAddressWithLEA() local 1815 MIB.addReg(0).addImm(1 << ShAmt) in convertToThreeAddressWithLEA() 1821 addRegOffset(MIB, leaInReg, true, 1); in convertToThreeAddressWithLEA() 1825 addRegOffset(MIB, leaInReg, true, -1); in convertToThreeAddressWithLEA() 1831 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); in convertToThreeAddressWithLEA() 1842 addRegReg(MIB, leaInReg, true, leaInReg, false); in convertToThreeAddressWithLEA() 1847 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); in convertToThreeAddressWithLEA() 1849 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) in convertToThreeAddressWithLEA() 1852 addRegReg(MIB, leaInReg, true, leaInReg2, true); in convertToThreeAddressWithLEA() 1860 MachineInstr *NewMI = MIB; in convertToThreeAddressWithLEA() [all …]
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 207 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument 226 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters() 241 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters() 253 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters() 295 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument 308 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() 340 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand() 342 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand() 343 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand() 350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand() [all …]
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D | InstrEmitter.h | 53 MachineInstrBuilder &MIB, 66 void AddRegisterOperand(MachineInstrBuilder &MIB, 77 void AddOperand(MachineInstrBuilder &MIB,
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/external/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 417 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() [all …]
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D | Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB = in emitThumbRegPlusImmInReg() local 133 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmInReg() 135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg() 137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg() 138 AddDefaultPred(MIB); in emitThumbRegPlusImmInReg() 242 const MachineInstrBuilder MIB = in emitThumbRegPlusImmediate() local 245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); in emitThumbRegPlusImmediate() 261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmediate() local 263 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmediate() 264 MIB.addReg(DestReg).addImm(ThisVal); in emitThumbRegPlusImmediate() [all …]
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D | Thumb2SizeReduction.cpp | 467 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local 469 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore() 470 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore() 473 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore() 478 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore() 483 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore() 486 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore() 489 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore() 491 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceLoadStore() 528 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), in ReduceSpecial() local [all …]
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D | ARMBaseInstrInfo.cpp | 681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg() local 682 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 684 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 685 AddDefaultPred(MIB); in copyPhysReg() 751 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, in AddDReg() argument 755 return MIB.addReg(Reg, State); in AddDReg() 758 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg() 759 return MIB.addReg(Reg, State, SubIdx); in AddDReg() 798 MachineInstrBuilder MIB = in storeRegToStackSlot() local 802 MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot() [all …]
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D | Thumb1FrameLowering.cpp | 318 MachineInstrBuilder MIB = in emitEpilogue() local 321 AddDefaultPred(MIB); in emitEpilogue() 322 MIB.copyImplicitOps(&*MBBI); in emitEpilogue() 342 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); in spillCalleeSavedRegisters() local 343 AddDefaultPred(MIB); in spillCalleeSavedRegisters() 361 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters() 363 MIB.setMIFlags(MachineInstr::FrameSetup); in spillCalleeSavedRegisters() 381 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); in restoreCalleeSavedRegisters() local 382 AddDefaultPred(MIB); in restoreCalleeSavedRegisters() 392 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); in restoreCalleeSavedRegisters() [all …]
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D | ARMFastISel.cpp | 224 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 226 const MachineInstrBuilder &MIB, 272 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { in AddOptionalDefs() argument 273 MachineInstr *MI = &*MIB; in AddOptionalDefs() 279 AddDefaultPred(MIB); in AddOptionalDefs() 286 AddDefaultT1CC(MIB); in AddOptionalDefs() 288 AddDefaultCC(MIB); in AddOptionalDefs() 290 return MIB; in AddOptionalDefs() 672 MachineInstrBuilder MIB; in ARMMaterializeGV() local 675 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) in ARMMaterializeGV() [all …]
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D | ARMBaseInstrInfo.h | 320 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { in AddDefaultPred() argument 321 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); in AddDefaultPred() 325 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { in AddDefaultCC() argument 326 return MIB.addReg(0); in AddDefaultCC() 330 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 336 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { in AddNoT1CC() argument 337 return MIB.addReg(0); in AddNoT1CC()
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D | ARMFrameLowering.cpp | 223 MachineInstrBuilder MIB = in emitPrologue() local 227 AddDefaultCC(AddDefaultPred(MIB)); in emitPrologue() 447 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); in emitEpilogue() local 449 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in emitEpilogue() 453 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in emitEpilogue() 458 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); in emitEpilogue() 628 MachineInstrBuilder MIB = in emitPushInst() local 632 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst() 634 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), in emitPushInst() local 639 AddDefaultPred(MIB); in emitPushInst() [all …]
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D | MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() local 296 MIB.addImm(LaneImm); in ExpandFPMLxInstruction() 297 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction() 299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2) in ExpandFPMLxInstruction() 304 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction() 309 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
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D | ARMInstrInfo.cpp | 125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, in runOnMachineFunction() local 129 MIB.addImm(0); in runOnMachineFunction() 130 AddDefaultPred(MIB); in runOnMachineFunction()
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D | ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) in MergeOps() local 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps() 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); in MergeOps() 777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple() local 784 MIB.addOperand(MI->getOperand(OpNum)); in MergeBaseUpdateLSMultiple() 787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in MergeBaseUpdateLSMultiple() 1082 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), in InsertLDR_STR() local 1086 MIB.addImm(Offset).addImm(Pred).addReg(PredReg); in InsertLDR_STR() 1088 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), in InsertLDR_STR() local 1092 MIB.addImm(Offset).addImm(Pred).addReg(PredReg); in InsertLDR_STR() [all …]
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D | Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) in InsertITInstructions() local 189 MachineBasicBlock::iterator InsertPos = MIB; in InsertITInstructions() 232 MIB.addImm(Mask); in InsertITInstructions()
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D | Thumb2InstrInfo.cpp | 279 MachineInstrBuilder MIB = in emitT2RegPlusImmediate() local 284 AddDefaultCC(MIB); in emitT2RegPlusImmediate() 411 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI); in rewriteT2FrameIndex() local 412 AddDefaultPred(MIB); in rewriteT2FrameIndex()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/llvm/lib/Target/Mips/ |
D | MipsInstrInfo.cpp | 68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) in emitFrameIndexDebugValue() local 70 return &*MIB; in emitFrameIndexDebugValue() 109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr() local 113 MIB.addReg(Cond[i].getReg()); in BuildCondBr() 115 MIB.addImm(Cond[i].getImm()); in BuildCondBr() 119 MIB.addMBB(TBB); in BuildCondBr()
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/external/llvm/lib/Target/R600/ |
D | R600InstrInfo.cpp | 78 MachineInstrBuilder MIB(*MF, MI); in getMovImmInstr() local 79 MIB.addReg(DstReg, RegState::Define); in getMovImmInstr() 80 MIB.addReg(AMDGPU::ALU_LITERAL_X); in getMovImmInstr() 81 MIB.addImm(Imm); in getMovImmInstr() 82 MIB.addReg(0); // PREDICATE_BIT in getMovImmInstr() 515 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in PredicateInstruction() local 516 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction() 655 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), in buildDefaultInstruction() local 659 MIB.addImm(0) // $update_exec_mask in buildDefaultInstruction() 662 MIB.addImm(1) // $write in buildDefaultInstruction() [all …]
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D | SIInstrInfo.cpp | 154 MachineInstrBuilder MIB(*MF, MI); in getMovImmInstr() local 155 MIB.addReg(DstReg, RegState::Define); in getMovImmInstr() 156 MIB.addImm(Imm); in getMovImmInstr()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FrameLowering.cpp | 213 MachineInstrBuilder MIB; in emitEpilogue() local 215 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm)); in emitEpilogue() 217 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in emitEpilogue() 221 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in emitEpilogue() 228 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx)); in emitEpilogue() 229 MIB.addReg(JumpTarget.getReg(), RegState::Kill); in emitEpilogue() 235 MIB->addOperand(MBBI->getOperand(i)); in emitEpilogue()
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D | AArch64InstrInfo.cpp | 123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) in emitFrameIndexDebugValue() local 127 return &*MIB; in emitFrameIndexDebugValue() 312 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); in InsertBranch() local 314 MIB.addOperand(Cond[i]); in InsertBranch() 315 MIB.addMBB(TBB); in InsertBranch() 319 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); in InsertBranch() local 321 MIB.addOperand(Cond[i]); in InsertBranch() 322 MIB.addMBB(TBB); in InsertBranch()
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/external/llvm/lib/CodeGen/ |
D | MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(), in finalizeBundle() local 112 Bundle.prepend(MIB); in finalizeBundle() 191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle() 200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
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/external/llvm/lib/Target/MBlaze/ |
D | MBlazeFrameLowering.cpp | 59 MachineInstr::mop_iterator MIB = MBB->operands_begin(); in replaceFrameIndexes() local 62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) { in replaceFrameIndexes() 99 MachineBasicBlock::iterator MIB = MBB->begin(); in analyzeFrameIndexes() local 121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) { in analyzeFrameIndexes() 171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) { in analyzeFrameIndexes()
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