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Searched refs:MO2 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp105 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
118 printRegName(O, MO2.getReg()); in printInst()
128 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
130 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
139 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
146 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) in printInst()
337 const MCOperand &MO2 = MI->getOperand(OpNum+1); in printSORegRegOperand() local
349 printRegName(O, MO2.getReg()); in printSORegRegOperand()
356 const MCOperand &MO2 = MI->getOperand(OpNum+1); in printSORegImmOperand() local
361 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
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/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.h84 const MachineOperand &MO2 = MI->getOperand(OpNo+1); in printMEMriOperand() local
88 << (int) MO2.getImm(); in printMEMriOperand()
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1); in printFrameIndexOperand() local
98 << MO2.getImm(); in printFrameIndexOperand()
DHexagonAsmPrinter.cpp256 const MachineOperand &MO2 = MI->getOperand(OpNo+1); in printAddrModeBasePlusOffset() local
260 << MO2.getImm(); in printAddrModeBasePlusOffset()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp726 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
728 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
942 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
945 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
946 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
947 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1046 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1061 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1164 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1165 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
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/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp1021 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); in getMachineSoRegOpValue() local
1022 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getMachineSoRegOpValue()
1063 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); in getMachineSoRegOpValue()
1068 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; in getMachineSoRegOpValue()
1251 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitLoadStoreInstruction() local
1258 if (!MO2.getReg()) { // is immediate in emitLoadStoreInstruction()
1268 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); in emitLoadStoreInstruction()
1270 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); in emitLoadStoreInstruction()
1322 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitMiscLoadStoreInstruction() local
1332 if (MO2.getReg()) { in emitMiscLoadStoreInstruction()
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DARMAsmPrinter.cpp992 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id in EmitJumpTable() local
996 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); in EmitJumpTable()
1038 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id in EmitJump2Table() local
1041 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); in EmitJump2Table()
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp129 const MCOperand &MO2 = MI.getOperand(OpNo+1); in getDirectBrEncoding() local
130 Fixups.push_back(MCFixup::Create(0, MO2.getExpr(), in getDirectBrEncoding()
/external/llvm/lib/Target/R600/
DR600InstrInfo.cpp479 MachineOperand &MO2 = Cond[2]; in ReverseBranchCondition() local
480 switch (MO2.getReg()) { in ReverseBranchCondition()
482 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
485 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()