/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86BaseInfo.h | 264 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator 563 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
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D | X86MCCodeEmitter.cpp | 689 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix() 1118 case X86II::MRM2r: case X86II::MRM3r: in EncodeInstruction()
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/external/llvm/utils/TableGen/ |
D | X86RecognizableInstr.cpp | 59 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator 711 case X86Local::MRM2r: in emitInstructionSpecifier() 822 case X86Local::MRM2r: in emitDecodePath() 865 case X86Local::MRM2r: in emitDecodePath() 946 case X86Local::MRM2r: in emitDecodePath()
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/external/llvm/lib/Target/X86/ |
D | X86InstrShiftRotate.td | 340 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), 342 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), 345 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), 348 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 350 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), 353 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 356 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 358 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), 361 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 365 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), [all …]
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D | X86InstrControl.td | 156 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 227 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
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D | X86InstrMMX.td | 415 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", 418 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", 421 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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D | X86InstrSystem.td | 384 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 479 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 482 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
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D | X86CodeEmitter.cpp | 1062 case X86II::MRM2r: case X86II::MRM3r: in emitVEXOpcodePrefix() 1356 case X86II::MRM2r: case X86II::MRM3r: in emitInstruction()
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D | X86InstrArithmetic.td | 420 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), 423 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), 426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), 429 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst", 1198 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
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D | X86InstrFormats.td | 25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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D | X86InstrSSE.td | 3844 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli, 3847 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli, 3850 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli, 3890 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli, 3893 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli, 3896 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli, 3936 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli, 3939 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli, 3942 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
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D | X86InstrInfo.td | 1656 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, 1658 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
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/external/llvm/test/TableGen/ |
D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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/external/llvm/docs/ |
D | TableGenFundamentals.rst | 718 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
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D | WritingAnLLVMBackend.rst | 1718 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
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