Home
last modified time | relevance | path

Searched refs:MRM7r (Results 1 – 11 of 11) sorted by relevance

/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp60 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || in needsModRMForDecode()
165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) in isRegFormat()
716 case X86Local::MRM7r: in emitInstructionSpecifier()
827 case X86Local::MRM7r: in emitDecodePath()
870 case X86Local::MRM7r: in emitDecodePath()
951 case X86Local::MRM7r: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h265 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
565 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp691 case X86II::MRM6r: case X86II::MRM7r: in EmitVEXOpcodePrefix()
1120 case X86II::MRM6r: case X86II::MRM7r: in EncodeInstruction()
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td222 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
226 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
230 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
234 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
240 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
244 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
249 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
253 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
260 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
264 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86CodeEmitter.cpp1064 case X86II::MRM6r: case X86II::MRM7r: in emitVEXOpcodePrefix()
1358 case X86II::MRM6r: case X86II::MRM7r: { in emitInstruction()
DX86InstrArithmetic.td335 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
338 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
341 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
345 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
1205 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
DX86InstrInfo.td1217 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1220 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1222 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
DX86InstrFormats.td27 def MRM6r : Format<22>; def MRM7r : Format<23>;
DX86InstrSSE.td3863 def VPSLLDQri : PDIi8<0x73, MRM7r,
3909 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3955 def PSLLDQri : PDIi8<0x73, MRM7r,
/external/llvm/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1720 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data