Home
last modified time | relevance | path

Searched refs:OutputArg (Results 1 – 25 of 35) sorted by relevance

12

/external/llvm/include/llvm/Target/
DTargetCallingConv.h136 struct OutputArg { struct
151 OutputArg() : IsFixed(false) {} in OutputArg() argument
152 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed, in OutputArg() function
DTargetLowering.h1945 SmallVector<ISD::OutputArg, 32> Outs;
2007 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, in CanLowerReturn() argument
2022 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, in LowerReturn() argument
2280 SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h123 const SmallVectorImpl<ISD::OutputArg> &Outs,
187 const SmallVectorImpl<ISD::OutputArg> &Outs,
194 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
DXCoreISelLowering.cpp899 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; in LowerCall()
931 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo()
1227 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
1237 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn()
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h542 const SmallVectorImpl<ISD::OutputArg> &Outs,
548 const SmallVectorImpl<ISD::OutputArg> &Outs,
589 const SmallVectorImpl<ISD::OutputArg> &Outs,
598 const SmallVectorImpl<ISD::OutputArg> &Outs,
606 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/Hexagon/
DHexagonCallingConvLower.h85 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
90 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
DHexagonCallingConvLower.cpp94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
131 Hexagon_CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> in AnalyzeCallOperands()
DHexagonISelLowering.h89 SmallVectorImpl<ISD::OutputArg> &Outs,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
DHexagonISelLowering.cpp303 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; in LowerCall()
1648 const SmallVectorImpl<ISD::OutputArg> &Outs, in IsEligibleForTailCallOptimization()
/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h202 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
208 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
213 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/Mips/
DMipsISelLowering.h224 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
236 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
395 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.h123 const SmallVectorImpl<ISD::OutputArg> &,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
DNVPTXISelLowering.cpp253 const SmallVectorImpl<ISD::OutputArg> &Outs, in getPrototype()
415 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; in LowerCall()
1202 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.h130 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
DMSP430ISelLowering.cpp280 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; in LowerCall()
408 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
462 const SmallVectorImpl<ISD::OutputArg> in LowerCCCCallTo()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h133 const SmallVectorImpl<ISD::OutputArg> &Outs,
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.h85 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/ARM/
DARMISelLowering.h502 const SmallVectorImpl<ISD::OutputArg> &Outs,
509 const SmallVectorImpl<ISD::OutputArg> &Outs,
515 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/X86/
DX86ISelLowering.h773 const SmallVectorImpl<ISD::OutputArg> &Outs,
863 const SmallVectorImpl<ISD::OutputArg> &Outs,
877 const SmallVectorImpl<ISD::OutputArg> &Outs,
/external/llvm/lib/Target/MBlaze/
DMBlazeISelLowering.h141 const SmallVectorImpl<ISD::OutputArg> &Outs,
DMBlazeISelLowering.cpp690 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; in LowerCall()
1018 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.h50 const SmallVectorImpl<ISD::OutputArg> &Outs,
DAMDGPUISelLowering.cpp82 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp68 SmallVector<ISD::OutputArg, 4> Outs; in set()

12