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Searched refs:RCX (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dabi-isel.ll58 ; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r..]]
59 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
87 ; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
88 ; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]])
94 ; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
95 ; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]])
101 ; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]]
102 ; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
130 ; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
131 ; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
[all …]
Dfp-stack-O0.ll11 ; CHECK-NEXT: movq %rsp, [[RCX:%r..]]
14 ; CHECK-NEXT: fstpt 16([[RCX]])
16 ; CHECK-NEXT: fstpt ([[RCX]])
Dor-address.ll50 ; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
51 ; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
52 ; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
53 ; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
/external/llvm/test/MC/X86/
Dintel-syntax.s23 mov RCX, QWORD PTR [0]
27 mov BYTE PTR [RDX + RCX], DIL
29 movzx EDI, WORD PTR [RCX + 2]
/external/llvm/lib/Target/X86/
DX86CallingConv.td38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
192 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
256 // Do not pass the sret argument in RCX, the Win64 thiscall calling
257 // convention requires "this" to be passed in RCX.
262 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
268 [RCX , RDX , R8 , R9 ]>>,
298 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
452 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
455 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
522 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
DX86SelectionDAGInfo.cpp133 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : in EmitTargetCodeForMemset()
152 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
231 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : in EmitTargetCodeForMemcpy()
DX86RegisterInfo.cpp539 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
551 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
588 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
624 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
660 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
661 return X86::RCX; in getX86SubSuperRegister()
DX86RegisterInfo.td130 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
337 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
339 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
341 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
360 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
DX86InstrCompiler.td335 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
366 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
367 let Uses = [AL,RCX,RDI] in
371 let Uses = [AX,RCX,RDI] in
375 let Uses = [RAX,RCX,RDI] in
380 let Uses = [RAX,RCX,RDI] in
412 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
757 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
DX86InstrSystem.td20 let Defs = [RAX, RCX, RDX] in
421 let Defs = [RDX, RAX], Uses = [RCX] in
424 let Uses = [RDX, RAX, RCX] in
DX86InstrControl.td105 let Uses = [RCX] in
DX86FastISel.cpp1198 CReg = X86::RCX; in X86SelectShift()
1575 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9 in FastLowerArguments()
DX86InstrInfo.td962 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1435 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
DX86FrameLowering.cpp103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, in findDeadCallerSavedReg()
DX86ISelLowering.cpp2084 X86::RCX, X86::RDX, X86::R8, X86::R9 in LowerFormalArguments()
2087 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 in LowerFormalArguments()
2417 case X86::XMM0: ShadowReg = X86::RCX; break; in LowerCall()
11005 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); in LowerEH_RETURN()
12328 Regs64bit ? X86::RCX : X86::ECX, in ReplaceNodeResults()
18338 case X86::CX: DestReg = X86::RCX; break; in getRegForInlineAsmConstraint()
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h40 #define RCX 88 macro
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h162 ENTRY(RCX) \
180 ENTRY(RCX) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c102 GENOFFSET(AMD64,amd64,RCX); in foo()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-amd64-linux.c359 SC2(rcx,RCX); in synth_ucontext()
/external/valgrind/main/memcheck/
Dmc_machine.c566 if (o == GOF(RCX) && is1248) return o; in get_otrack_shadow_offset_wrk()
608 if (o == 1+ GOF(RCX) && szB == 1) return GOF(DFLAG); in get_otrack_shadow_offset_wrk()
662 if (o == 4+ GOF(RCX) && sz == 4) return GOF(RCX); in get_otrack_shadow_offset_wrk()
/external/strace/
Dutil.c1421 # define arg1_offset ((long)(8*(current_personality ? RCX : RSI)))
Dprocess.c2685 { 8*RCX, "8*RCX" },
Dsyscall.c2224 {RBX,RCX,RDX,RSI,RDI,RBP} /* i386 ABI */ in syscall_enter()
/external/llvm/docs/
DTableGenFundamentals.rst180 R15B, R15D, R15W, R8, R8B, R8D, R8W, R9, R9B, R9D, R9W, RAX, RBP, RBX, RCX, RDI,