1//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the various pseudo instructions used by the compiler, 11// as well as Pat patterns used during instruction selection. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Pattern Matching Support 17 18def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue()); 21}]>; 22 23def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue()); 26}]>; 27 28 29//===----------------------------------------------------------------------===// 30// Random Pseudo Instructions. 31 32// PIC base construction. This expands to code that looks like this: 33// call $next_inst 34// popl %destreg" 35let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41// a stack adjustment and the codegen must know that they may modify the stack 42// pointer before prolog-epilog rewriting occurs. 43// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44// sub / add which can clobber EFLAGS. 45let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), 47 "#ADJCALLSTACKDOWN", 48 [(X86callseq_start timm:$amt)]>, 49 Requires<[In32BitMode]>; 50def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[In32BitMode]>; 54} 55 56// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 57// a stack adjustment and the codegen must know that they may modify the stack 58// pointer before prolog-epilog rewriting occurs. 59// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 60// sub / add which can clobber EFLAGS. 61let Defs = [RSP, EFLAGS], Uses = [RSP] in { 62def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt), 63 "#ADJCALLSTACKDOWN", 64 [(X86callseq_start timm:$amt)]>, 65 Requires<[In64BitMode]>; 66def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 67 "#ADJCALLSTACKUP", 68 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 69 Requires<[In64BitMode]>; 70} 71 72 73 74// x86-64 va_start lowering magic. 75let usesCustomInserter = 1 in { 76def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 77 (outs), 78 (ins GR8:$al, 79 i64imm:$regsavefi, i64imm:$offset, 80 variable_ops), 81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 82 [(X86vastart_save_xmm_regs GR8:$al, 83 imm:$regsavefi, 84 imm:$offset)]>; 85 86// The VAARG_64 pseudo-instruction takes the address of the va_list, 87// and places the address of the next argument into a register. 88let Defs = [EFLAGS] in 89def VAARG_64 : I<0, Pseudo, 90 (outs GR64:$dst), 91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 92 "#VAARG_64 $dst, $ap, $size, $mode, $align", 93 [(set GR64:$dst, 94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 95 (implicit EFLAGS)]>; 96 97// Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 98// targets. These calls are needed to probe the stack when allocating more than 99// 4k bytes in one go. Touching the stack at 4K increments is necessary to 100// ensure that the guard pages used by the OS virtual memory manager are 101// allocated in correct sequence. 102// The main point of having separate instruction are extra unmodelled effects 103// (compared to ordinary calls) like stack pointer change. 104 105let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 107 "# dynamic stack allocation", 108 [(X86WinAlloca)]>; 109 110// When using segmented stacks these are lowered into instructions which first 111// check if the current stacklet has enough free memory. If it does, memory is 112// allocated by bumping the stack pointer. Otherwise memory is allocated from 113// the heap. 114 115let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 116def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 117 "# variable sized alloca for segmented stacks", 118 [(set GR32:$dst, 119 (X86SegAlloca GR32:$size))]>, 120 Requires<[In32BitMode]>; 121 122let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 123def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 124 "# variable sized alloca for segmented stacks", 125 [(set GR64:$dst, 126 (X86SegAlloca GR64:$size))]>, 127 Requires<[In64BitMode]>; 128} 129 130// The MSVC runtime contains an _ftol2 routine for converting floating-point 131// to integer values. It has a strange calling convention: the input is 132// popped from the x87 stack, and the return value is given in EDX:EAX. No 133// other registers (aside from flags) are touched. 134// Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80 135// variant is unnecessary. 136 137let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in { 138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src), 139 "# win32 fptoui", 140 [(X86WinFTOL RFP32:$src)]>, 141 Requires<[In32BitMode]>; 142 143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src), 144 "# win32 fptoui", 145 [(X86WinFTOL RFP64:$src)]>, 146 Requires<[In32BitMode]>; 147} 148 149//===----------------------------------------------------------------------===// 150// EH Pseudo Instructions 151// 152let isTerminator = 1, isReturn = 1, isBarrier = 1, 153 hasCtrlDep = 1, isCodeGenOnly = 1 in { 154def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 155 "ret\t#eh_return, addr: $addr", 156 [(X86ehret GR32:$addr)], IIC_RET>; 157 158} 159 160let isTerminator = 1, isReturn = 1, isBarrier = 1, 161 hasCtrlDep = 1, isCodeGenOnly = 1 in { 162def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 163 "ret\t#eh_return, addr: $addr", 164 [(X86ehret GR64:$addr)], IIC_RET>; 165 166} 167 168let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 169 usesCustomInserter = 1 in { 170 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 171 "#EH_SJLJ_SETJMP32", 172 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 173 Requires<[In32BitMode]>; 174 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 175 "#EH_SJLJ_SETJMP64", 176 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 177 Requires<[In64BitMode]>; 178 let isTerminator = 1 in { 179 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 180 "#EH_SJLJ_LONGJMP32", 181 [(X86eh_sjlj_longjmp addr:$buf)]>, 182 Requires<[In32BitMode]>; 183 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 184 "#EH_SJLJ_LONGJMP64", 185 [(X86eh_sjlj_longjmp addr:$buf)]>, 186 Requires<[In64BitMode]>; 187 } 188} 189 190let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 191 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 192 "#EH_SjLj_Setup\t$dst", []>; 193} 194 195//===----------------------------------------------------------------------===// 196// Pseudo instructions used by segmented stacks. 197// 198 199// This is lowered into a RET instruction by MCInstLower. We need 200// this so that we don't have to have a MachineBasicBlock which ends 201// with a RET and also has successors. 202let isPseudo = 1 in { 203def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 204 "", []>; 205 206// This instruction is lowered to a RET followed by a MOV. The two 207// instructions are not generated on a higher level since then the 208// verifier sees a MachineBasicBlock ending with a non-terminator. 209def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 210 "", []>; 211} 212 213//===----------------------------------------------------------------------===// 214// Alias Instructions 215//===----------------------------------------------------------------------===// 216 217// Alias instructions that map movr0 to xor. 218// FIXME: remove when we can teach regalloc that xor reg, reg is ok. 219// FIXME: Set encoding to pseudo. 220let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 221 isCodeGenOnly = 1 in { 222def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "", 223 [(set GR8:$dst, 0)], IIC_ALU_NONMEM>; 224 225// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller 226// encoding and avoids a partial-register update sometimes, but doing so 227// at isel time interferes with rematerialization in the current register 228// allocator. For now, this is rewritten when the instruction is lowered 229// to an MCInst. 230def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), 231 "", 232 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize; 233 234// FIXME: Set encoding to pseudo. 235def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", 236 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>; 237} 238 239// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a 240// smaller encoding, but doing so at isel time interferes with rematerialization 241// in the current register allocator. For now, this is rewritten when the 242// instruction is lowered to an MCInst. 243// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove 244// when we have a better way to specify isel priority. 245let Defs = [EFLAGS], isCodeGenOnly=1, 246 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in 247def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "", 248 [(set GR64:$dst, 0)], IIC_ALU_NONMEM>; 249 250// Materialize i64 constant where top 32-bits are zero. This could theoretically 251// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 252// that would make it more difficult to rematerialize. 253let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 254 isCodeGenOnly = 1 in 255def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), 256 "", [(set GR64:$dst, i64immZExt32:$src)], 257 IIC_ALU_NONMEM>; 258 259// Use sbb to materialize carry bit. 260let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1 in { 261// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 262// However, Pat<> can't replicate the destination reg into the inputs of the 263// result. 264def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 265 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 266def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 267 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 268def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 269 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 270def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 271 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 272} // isCodeGenOnly 273 274 275def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 276 (SETB_C16r)>; 277def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 278 (SETB_C32r)>; 279def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 280 (SETB_C64r)>; 281 282def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 283 (SETB_C16r)>; 284def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 285 (SETB_C32r)>; 286def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 287 (SETB_C64r)>; 288 289// We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 290// will be eliminated and that the sbb can be extended up to a wider type. When 291// this happens, it is great. However, if we are left with an 8-bit sbb and an 292// and, we might as well just match it as a setb. 293def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 294 (SETBr)>; 295 296// (add OP, SETB) -> (adc OP, 0) 297def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 298 (ADC8ri GR8:$op, 0)>; 299def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 300 (ADC32ri8 GR32:$op, 0)>; 301def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 302 (ADC64ri8 GR64:$op, 0)>; 303 304// (sub OP, SETB) -> (sbb OP, 0) 305def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 306 (SBB8ri GR8:$op, 0)>; 307def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 308 (SBB32ri8 GR32:$op, 0)>; 309def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 310 (SBB64ri8 GR64:$op, 0)>; 311 312// (sub OP, SETCC_CARRY) -> (adc OP, 0) 313def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 314 (ADC8ri GR8:$op, 0)>; 315def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 316 (ADC32ri8 GR32:$op, 0)>; 317def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 318 (ADC64ri8 GR64:$op, 0)>; 319 320//===----------------------------------------------------------------------===// 321// String Pseudo Instructions 322// 323let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 324def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 325 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 326 Requires<[In32BitMode]>; 327def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 328 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize, 329 Requires<[In32BitMode]>; 330def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 331 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, 332 Requires<[In32BitMode]>; 333} 334 335let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 336def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 337 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 338 Requires<[In64BitMode]>; 339def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 340 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize, 341 Requires<[In64BitMode]>; 342def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 343 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, 344 Requires<[In64BitMode]>; 345def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 346 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 347 Requires<[In64BitMode]>; 348} 349 350// FIXME: Should use "(X86rep_stos AL)" as the pattern. 351let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 352 let Uses = [AL,ECX,EDI] in 353 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 354 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 355 Requires<[In32BitMode]>; 356 let Uses = [AX,ECX,EDI] in 357 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 358 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize, 359 Requires<[In32BitMode]>; 360 let Uses = [EAX,ECX,EDI] in 361 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 362 [(X86rep_stos i32)], IIC_REP_STOS>, REP, 363 Requires<[In32BitMode]>; 364} 365 366let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 367 let Uses = [AL,RCX,RDI] in 368 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 369 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 370 Requires<[In64BitMode]>; 371 let Uses = [AX,RCX,RDI] in 372 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 373 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize, 374 Requires<[In64BitMode]>; 375 let Uses = [RAX,RCX,RDI] in 376 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 377 [(X86rep_stos i32)], IIC_REP_STOS>, REP, 378 Requires<[In64BitMode]>; 379 380 let Uses = [RAX,RCX,RDI] in 381 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 382 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 383 Requires<[In64BitMode]>; 384} 385 386//===----------------------------------------------------------------------===// 387// Thread Local Storage Instructions 388// 389 390// ELF TLS Support 391// All calls clobber the non-callee saved registers. ESP is marked as 392// a use to prevent stack-pointer assignments that appear immediately 393// before calls from potentially appearing dead. 394let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, 395 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 396 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 397 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 398 Uses = [ESP] in { 399def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 400 "# TLS_addr32", 401 [(X86tlsaddr tls32addr:$sym)]>, 402 Requires<[In32BitMode]>; 403def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 404 "# TLS_base_addr32", 405 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 406 Requires<[In32BitMode]>; 407} 408 409// All calls clobber the non-callee saved registers. RSP is marked as 410// a use to prevent stack-pointer assignments that appear immediately 411// before calls from potentially appearing dead. 412let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 413 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, 414 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 415 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 416 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 417 Uses = [RSP] in { 418def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 419 "# TLS_addr64", 420 [(X86tlsaddr tls64addr:$sym)]>, 421 Requires<[In64BitMode]>; 422def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 423 "# TLS_base_addr64", 424 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 425 Requires<[In64BitMode]>; 426} 427 428// Darwin TLS Support 429// For i386, the address of the thunk is passed on the stack, on return the 430// address of the variable is in %eax. %ecx is trashed during the function 431// call. All other registers are preserved. 432let Defs = [EAX, ECX, EFLAGS], 433 Uses = [ESP], 434 usesCustomInserter = 1 in 435def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 436 "# TLSCall_32", 437 [(X86TLSCall addr:$sym)]>, 438 Requires<[In32BitMode]>; 439 440// For x86_64, the address of the thunk is passed in %rdi, on return 441// the address of the variable is in %rax. All other registers are preserved. 442let Defs = [RAX, EFLAGS], 443 Uses = [RSP, RDI], 444 usesCustomInserter = 1 in 445def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 446 "# TLSCall_64", 447 [(X86TLSCall addr:$sym)]>, 448 Requires<[In64BitMode]>; 449 450 451//===----------------------------------------------------------------------===// 452// Conditional Move Pseudo Instructions 453 454// X86 doesn't have 8-bit conditional moves. Use a customInserter to 455// emit control flow. An alternative to this is to mark i8 SELECT as Promote, 456// however that requires promoting the operands, and can induce additional 457// i8 register pressure. 458let usesCustomInserter = 1, Uses = [EFLAGS] in { 459def CMOV_GR8 : I<0, Pseudo, 460 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond), 461 "#CMOV_GR8 PSEUDO!", 462 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2, 463 imm:$cond, EFLAGS))]>; 464 465let Predicates = [NoCMov] in { 466def CMOV_GR32 : I<0, Pseudo, 467 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond), 468 "#CMOV_GR32* PSEUDO!", 469 [(set GR32:$dst, 470 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>; 471def CMOV_GR16 : I<0, Pseudo, 472 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond), 473 "#CMOV_GR16* PSEUDO!", 474 [(set GR16:$dst, 475 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>; 476} // Predicates = [NoCMov] 477 478// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 479// SSE1. 480let Predicates = [FPStackf32] in 481def CMOV_RFP32 : I<0, Pseudo, 482 (outs RFP32:$dst), 483 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond), 484 "#CMOV_RFP32 PSEUDO!", 485 [(set RFP32:$dst, 486 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond, 487 EFLAGS))]>; 488// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 489// SSE2. 490let Predicates = [FPStackf64] in 491def CMOV_RFP64 : I<0, Pseudo, 492 (outs RFP64:$dst), 493 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond), 494 "#CMOV_RFP64 PSEUDO!", 495 [(set RFP64:$dst, 496 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond, 497 EFLAGS))]>; 498def CMOV_RFP80 : I<0, Pseudo, 499 (outs RFP80:$dst), 500 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond), 501 "#CMOV_RFP80 PSEUDO!", 502 [(set RFP80:$dst, 503 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond, 504 EFLAGS))]>; 505} // UsesCustomInserter = 1, Uses = [EFLAGS] 506 507 508//===----------------------------------------------------------------------===// 509// Atomic Instruction Pseudo Instructions 510//===----------------------------------------------------------------------===// 511 512// Pseudo atomic instructions 513 514multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> { 515 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in { 516 let Defs = [EFLAGS, AL] in 517 def NAME#8 : I<0, Pseudo, (outs GR8:$dst), 518 (ins i8mem:$ptr, GR8:$val), 519 !strconcat(mnemonic, "8 PSEUDO!"), []>; 520 let Defs = [EFLAGS, AX] in 521 def NAME#16 : I<0, Pseudo,(outs GR16:$dst), 522 (ins i16mem:$ptr, GR16:$val), 523 !strconcat(mnemonic, "16 PSEUDO!"), []>; 524 let Defs = [EFLAGS, EAX] in 525 def NAME#32 : I<0, Pseudo, (outs GR32:$dst), 526 (ins i32mem:$ptr, GR32:$val), 527 !strconcat(mnemonic, "32 PSEUDO!"), []>; 528 let Defs = [EFLAGS, RAX] in 529 def NAME#64 : I<0, Pseudo, (outs GR64:$dst), 530 (ins i64mem:$ptr, GR64:$val), 531 !strconcat(mnemonic, "64 PSEUDO!"), []>; 532 } 533} 534 535multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> { 536 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val), 537 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>; 538 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val), 539 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>; 540 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val), 541 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>; 542 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val), 543 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>; 544} 545 546// Atomic exchange, and, or, xor 547defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">; 548defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">; 549defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">; 550defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">; 551defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">; 552defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">; 553defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">; 554defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">; 555 556defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">; 557defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">; 558defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">; 559defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">; 560defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">; 561defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">; 562defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">; 563defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">; 564 565multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> { 566 let usesCustomInserter = 1, Defs = [EFLAGS, EAX, EDX], 567 mayLoad = 1, mayStore = 1, hasSideEffects = 0 in 568 def NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), 569 (ins i64mem:$ptr, GR32:$val1, GR32:$val2), 570 !strconcat(mnemonic, "6432 PSEUDO!"), []>; 571} 572 573defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">; 574defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">; 575defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">; 576defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">; 577defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">; 578defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">; 579defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">; 580defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">; 581defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">; 582defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">; 583defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">; 584 585//===----------------------------------------------------------------------===// 586// Normal-Instructions-With-Lock-Prefix Pseudo Instructions 587//===----------------------------------------------------------------------===// 588 589// FIXME: Use normal instructions and add lock prefix dynamically. 590 591// Memory barriers 592 593// TODO: Get this to fold the constant into the instruction. 594let isCodeGenOnly = 1, Defs = [EFLAGS] in 595def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 596 "or{l}\t{$zero, $dst|$dst, $zero}", 597 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK; 598 599let hasSideEffects = 1 in 600def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 601 "#MEMBARRIER", 602 [(X86MemBarrier)]>; 603 604// RegOpc corresponds to the mr version of the instruction 605// ImmOpc corresponds to the mi version of the instruction 606// ImmOpc8 corresponds to the mi8 version of the instruction 607// ImmMod corresponds to the instruction format of the mi and mi8 versions 608multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 609 Format ImmMod, string mnemonic> { 610let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 611 612def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 613 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 614 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 615 !strconcat(mnemonic, "{b}\t", 616 "{$src2, $dst|$dst, $src2}"), 617 [], IIC_ALU_NONMEM>, LOCK; 618def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 619 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 620 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 621 !strconcat(mnemonic, "{w}\t", 622 "{$src2, $dst|$dst, $src2}"), 623 [], IIC_ALU_NONMEM>, OpSize, LOCK; 624def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 625 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 626 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 627 !strconcat(mnemonic, "{l}\t", 628 "{$src2, $dst|$dst, $src2}"), 629 [], IIC_ALU_NONMEM>, LOCK; 630def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 631 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 632 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 633 !strconcat(mnemonic, "{q}\t", 634 "{$src2, $dst|$dst, $src2}"), 635 [], IIC_ALU_NONMEM>, LOCK; 636 637def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 638 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 639 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 640 !strconcat(mnemonic, "{b}\t", 641 "{$src2, $dst|$dst, $src2}"), 642 [], IIC_ALU_MEM>, LOCK; 643 644def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 645 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 646 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 647 !strconcat(mnemonic, "{w}\t", 648 "{$src2, $dst|$dst, $src2}"), 649 [], IIC_ALU_MEM>, OpSize, LOCK; 650 651def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 652 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 653 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 654 !strconcat(mnemonic, "{l}\t", 655 "{$src2, $dst|$dst, $src2}"), 656 [], IIC_ALU_MEM>, LOCK; 657 658def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 659 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 660 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 661 !strconcat(mnemonic, "{q}\t", 662 "{$src2, $dst|$dst, $src2}"), 663 [], IIC_ALU_MEM>, LOCK; 664 665def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 666 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 667 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 668 !strconcat(mnemonic, "{w}\t", 669 "{$src2, $dst|$dst, $src2}"), 670 [], IIC_ALU_MEM>, OpSize, LOCK; 671def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 672 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 673 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 674 !strconcat(mnemonic, "{l}\t", 675 "{$src2, $dst|$dst, $src2}"), 676 [], IIC_ALU_MEM>, LOCK; 677def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 678 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 679 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 680 !strconcat(mnemonic, "{q}\t", 681 "{$src2, $dst|$dst, $src2}"), 682 [], IIC_ALU_MEM>, LOCK; 683 684} 685 686} 687 688defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 689defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 690defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 691defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 692defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 693 694// Optimized codegen when the non-memory output is not used. 695multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 696 string mnemonic> { 697let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { 698 699def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 700 !strconcat(mnemonic, "{b}\t$dst"), 701 [], IIC_UNARY_MEM>, LOCK; 702def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 703 !strconcat(mnemonic, "{w}\t$dst"), 704 [], IIC_UNARY_MEM>, OpSize, LOCK; 705def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 706 !strconcat(mnemonic, "{l}\t$dst"), 707 [], IIC_UNARY_MEM>, LOCK; 708def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 709 !strconcat(mnemonic, "{q}\t$dst"), 710 [], IIC_UNARY_MEM>, LOCK; 711} 712} 713 714defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">; 715defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">; 716 717// Atomic compare and swap. 718multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 719 SDPatternOperator frag, X86MemOperand x86memop, 720 InstrItinClass itin> { 721let isCodeGenOnly = 1 in { 722 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 723 !strconcat(mnemonic, "\t$ptr"), 724 [(frag addr:$ptr)], itin>, TB, LOCK; 725} 726} 727 728multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 729 string mnemonic, SDPatternOperator frag, 730 InstrItinClass itin8, InstrItinClass itin> { 731let isCodeGenOnly = 1 in { 732 let Defs = [AL, EFLAGS], Uses = [AL] in 733 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 734 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 735 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 736 let Defs = [AX, EFLAGS], Uses = [AX] in 737 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 738 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 739 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK; 740 let Defs = [EAX, EFLAGS], Uses = [EAX] in 741 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 742 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 743 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK; 744 let Defs = [RAX, EFLAGS], Uses = [RAX] in 745 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 746 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 747 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 748} 749} 750 751let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { 752defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 753 X86cas8, i64mem, 754 IIC_CMPX_LOCK_8B>; 755} 756 757let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 758 Predicates = [HasCmpxchg16b] in { 759defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 760 X86cas16, i128mem, 761 IIC_CMPX_LOCK_16B>, REX_W; 762} 763 764defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 765 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 766 767// Atomic exchange and add 768multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 769 string frag, 770 InstrItinClass itin8, InstrItinClass itin> { 771 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in { 772 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 773 (ins GR8:$val, i8mem:$ptr), 774 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 775 [(set GR8:$dst, 776 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 777 itin8>; 778 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 779 (ins GR16:$val, i16mem:$ptr), 780 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 781 [(set 782 GR16:$dst, 783 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 784 itin>, OpSize; 785 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 786 (ins GR32:$val, i32mem:$ptr), 787 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 788 [(set 789 GR32:$dst, 790 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 791 itin>; 792 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 793 (ins GR64:$val, i64mem:$ptr), 794 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 795 [(set 796 GR64:$dst, 797 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 798 itin>; 799 } 800} 801 802defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 803 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 804 TB, LOCK; 805 806def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 807 "#ACQUIRE_MOV PSEUDO!", 808 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 809def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 810 "#ACQUIRE_MOV PSEUDO!", 811 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 812def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 813 "#ACQUIRE_MOV PSEUDO!", 814 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 815def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 816 "#ACQUIRE_MOV PSEUDO!", 817 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 818 819def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 820 "#RELEASE_MOV PSEUDO!", 821 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 822def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 823 "#RELEASE_MOV PSEUDO!", 824 [(atomic_store_16 addr:$dst, GR16:$src)]>; 825def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 826 "#RELEASE_MOV PSEUDO!", 827 [(atomic_store_32 addr:$dst, GR32:$src)]>; 828def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 829 "#RELEASE_MOV PSEUDO!", 830 [(atomic_store_64 addr:$dst, GR64:$src)]>; 831 832//===----------------------------------------------------------------------===// 833// Conditional Move Pseudo Instructions. 834//===----------------------------------------------------------------------===// 835 836 837// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after 838// instruction selection into a branch sequence. 839let Uses = [EFLAGS], usesCustomInserter = 1 in { 840 def CMOV_FR32 : I<0, Pseudo, 841 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond), 842 "#CMOV_FR32 PSEUDO!", 843 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond, 844 EFLAGS))]>; 845 def CMOV_FR64 : I<0, Pseudo, 846 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond), 847 "#CMOV_FR64 PSEUDO!", 848 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond, 849 EFLAGS))]>; 850 def CMOV_V4F32 : I<0, Pseudo, 851 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 852 "#CMOV_V4F32 PSEUDO!", 853 [(set VR128:$dst, 854 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, 855 EFLAGS)))]>; 856 def CMOV_V2F64 : I<0, Pseudo, 857 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 858 "#CMOV_V2F64 PSEUDO!", 859 [(set VR128:$dst, 860 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 861 EFLAGS)))]>; 862 def CMOV_V2I64 : I<0, Pseudo, 863 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond), 864 "#CMOV_V2I64 PSEUDO!", 865 [(set VR128:$dst, 866 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond, 867 EFLAGS)))]>; 868 def CMOV_V8F32 : I<0, Pseudo, 869 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 870 "#CMOV_V8F32 PSEUDO!", 871 [(set VR256:$dst, 872 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, 873 EFLAGS)))]>; 874 def CMOV_V4F64 : I<0, Pseudo, 875 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 876 "#CMOV_V4F64 PSEUDO!", 877 [(set VR256:$dst, 878 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 879 EFLAGS)))]>; 880 def CMOV_V4I64 : I<0, Pseudo, 881 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond), 882 "#CMOV_V4I64 PSEUDO!", 883 [(set VR256:$dst, 884 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond, 885 EFLAGS)))]>; 886} 887 888 889//===----------------------------------------------------------------------===// 890// DAG Pattern Matching Rules 891//===----------------------------------------------------------------------===// 892 893// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 894def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 895def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 896def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 897def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 898def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 899def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 900 901def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 902 (ADD32ri GR32:$src1, tconstpool:$src2)>; 903def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 904 (ADD32ri GR32:$src1, tjumptable:$src2)>; 905def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 906 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 907def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 908 (ADD32ri GR32:$src1, texternalsym:$src2)>; 909def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 910 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 911 912def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 913 (MOV32mi addr:$dst, tglobaladdr:$src)>; 914def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 915 (MOV32mi addr:$dst, texternalsym:$src)>; 916def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 917 (MOV32mi addr:$dst, tblockaddress:$src)>; 918 919 920 921// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 922// code model mode, should use 'movabs'. FIXME: This is really a hack, the 923// 'movabs' predicate should handle this sort of thing. 924def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 925 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 926def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 927 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 928def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 929 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 930def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 931 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 932def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 933 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 934 935// In static codegen with small code model, we can get the address of a label 936// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of 937// the MOV64ri64i32 should accept these. 938def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 939 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>; 940def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 941 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>; 942def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 943 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>; 944def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 945 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>; 946def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 947 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>; 948 949// In kernel code model, we can get the address of a label 950// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 951// the MOV64ri32 should accept these. 952def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 953 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 954def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 955 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 956def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 957 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 958def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 959 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 960def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 961 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 962 963// If we have small model and -static mode, it is safe to store global addresses 964// directly as immediates. FIXME: This is really a hack, the 'imm' predicate 965// for MOV64mi32 should handle this sort of thing. 966def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 967 (MOV64mi32 addr:$dst, tconstpool:$src)>, 968 Requires<[NearData, IsStatic]>; 969def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 970 (MOV64mi32 addr:$dst, tjumptable:$src)>, 971 Requires<[NearData, IsStatic]>; 972def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 973 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 974 Requires<[NearData, IsStatic]>; 975def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 976 (MOV64mi32 addr:$dst, texternalsym:$src)>, 977 Requires<[NearData, IsStatic]>; 978def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 979 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 980 Requires<[NearData, IsStatic]>; 981 982 983 984// Calls 985 986// tls has some funny stuff here... 987// This corresponds to movabs $foo@tpoff, %rax 988def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 989 (MOV64ri tglobaltlsaddr :$dst)>; 990// This corresponds to add $foo@tpoff, %rax 991def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 992 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 993// This corresponds to mov foo@tpoff(%rbx), %eax 994def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), 995 (MOV64rm tglobaltlsaddr :$dst)>; 996 997 998// Direct PC relative function call for small code model. 32-bit displacement 999// sign extended to 64-bit. 1000def : Pat<(X86call (i64 tglobaladdr:$dst)), 1001 (CALL64pcrel32 tglobaladdr:$dst)>; 1002def : Pat<(X86call (i64 texternalsym:$dst)), 1003 (CALL64pcrel32 texternalsym:$dst)>; 1004 1005// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1006// can never use callee-saved registers. That is the purpose of the GR64_TC 1007// register classes. 1008// 1009// The only volatile register that is never used by the calling convention is 1010// %r11. This happens when calling a vararg function with 6 arguments. 1011// 1012// Match an X86tcret that uses less than 7 volatile registers. 1013def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1014 (X86tcret node:$ptr, node:$off), [{ 1015 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1016 unsigned NumRegs = 0; 1017 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1018 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1019 return false; 1020 return true; 1021}]>; 1022 1023def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1024 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1025 Requires<[In32BitMode]>; 1026 1027// FIXME: This is disabled for 32-bit PIC mode because the global base 1028// register which is part of the address mode may be assigned a 1029// callee-saved register. 1030def : Pat<(X86tcret (load addr:$dst), imm:$off), 1031 (TCRETURNmi addr:$dst, imm:$off)>, 1032 Requires<[In32BitMode, IsNotPIC]>; 1033 1034def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1035 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1036 Requires<[In32BitMode]>; 1037 1038def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1039 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1040 Requires<[In32BitMode]>; 1041 1042def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1043 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1044 Requires<[In64BitMode]>; 1045 1046// Don't fold loads into X86tcret requiring more than 6 regs. 1047// There wouldn't be enough scratch registers for base+index. 1048def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1049 (TCRETURNmi64 addr:$dst, imm:$off)>, 1050 Requires<[In64BitMode]>; 1051 1052def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1053 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1054 Requires<[In64BitMode]>; 1055 1056def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1057 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1058 Requires<[In64BitMode]>; 1059 1060// Normal calls, with various flavors of addresses. 1061def : Pat<(X86call (i32 tglobaladdr:$dst)), 1062 (CALLpcrel32 tglobaladdr:$dst)>; 1063def : Pat<(X86call (i32 texternalsym:$dst)), 1064 (CALLpcrel32 texternalsym:$dst)>; 1065def : Pat<(X86call (i32 imm:$dst)), 1066 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1067 1068// Comparisons. 1069 1070// TEST R,R is smaller than CMP R,0 1071def : Pat<(X86cmp GR8:$src1, 0), 1072 (TEST8rr GR8:$src1, GR8:$src1)>; 1073def : Pat<(X86cmp GR16:$src1, 0), 1074 (TEST16rr GR16:$src1, GR16:$src1)>; 1075def : Pat<(X86cmp GR32:$src1, 0), 1076 (TEST32rr GR32:$src1, GR32:$src1)>; 1077def : Pat<(X86cmp GR64:$src1, 0), 1078 (TEST64rr GR64:$src1, GR64:$src1)>; 1079 1080// Conditional moves with folded loads with operands swapped and conditions 1081// inverted. 1082multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1083 Instruction Inst64> { 1084 let Predicates = [HasCMov] in { 1085 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1086 (Inst16 GR16:$src2, addr:$src1)>; 1087 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1088 (Inst32 GR32:$src2, addr:$src1)>; 1089 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1090 (Inst64 GR64:$src2, addr:$src1)>; 1091 } 1092} 1093 1094defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1095defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1096defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1097defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1098defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1099defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1100defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1101defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1102defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1103defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1104defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1105defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1106defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1107defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1108defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1109defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1110 1111// zextload bool -> zextload byte 1112def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1113def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1114def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1115def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 1116 1117// extload bool -> extload byte 1118// When extloading from 16-bit and smaller memory locations into 64-bit 1119// registers, use zero-extending loads so that the entire 64-bit register is 1120// defined, avoiding partial-register updates. 1121 1122def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1123def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1124def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1125def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1126def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1127def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1128 1129def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; 1130def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; 1131def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; 1132// For other extloads, use subregs, since the high contents of the register are 1133// defined after an extload. 1134def : Pat<(extloadi64i32 addr:$src), 1135 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), 1136 sub_32bit)>; 1137 1138// anyext. Define these to do an explicit zero-extend to 1139// avoid partial-register updates. 1140def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1141 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1142def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1143 1144// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1145def : Pat<(i32 (anyext GR16:$src)), 1146 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1147 1148def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>; 1149def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>; 1150def : Pat<(i64 (anyext GR32:$src)), 1151 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1152 1153 1154// Any instruction that defines a 32-bit result leaves the high half of the 1155// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1156// be copying from a truncate. And x86's cmov doesn't do anything if the 1157// condition is false. But any other 32-bit operation will zero-extend 1158// up to 64 bits. 1159def def32 : PatLeaf<(i32 GR32:$src), [{ 1160 return N->getOpcode() != ISD::TRUNCATE && 1161 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1162 N->getOpcode() != ISD::CopyFromReg && 1163 N->getOpcode() != X86ISD::CMOV; 1164}]>; 1165 1166// In the case of a 32-bit def that is known to implicitly zero-extend, 1167// we can use a SUBREG_TO_REG. 1168def : Pat<(i64 (zext def32:$src)), 1169 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1170 1171//===----------------------------------------------------------------------===// 1172// Pattern match OR as ADD 1173//===----------------------------------------------------------------------===// 1174 1175// If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1176// 3-addressified into an LEA instruction to avoid copies. However, we also 1177// want to finally emit these instructions as an or at the end of the code 1178// generator to make the generated code easier to read. To do this, we select 1179// into "disjoint bits" pseudo ops. 1180 1181// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1182def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1183 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1184 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1185 1186 APInt KnownZero0, KnownOne0; 1187 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1188 APInt KnownZero1, KnownOne1; 1189 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1190 return (~KnownZero0 & ~KnownZero1) == 0; 1191}]>; 1192 1193 1194// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1195let AddedComplexity = 5 in { // Try this before the selecting to OR 1196 1197let isConvertibleToThreeAddress = 1, 1198 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1199let isCommutable = 1 in { 1200def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1201 "", // orw/addw REG, REG 1202 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1203def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1204 "", // orl/addl REG, REG 1205 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1206def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1207 "", // orq/addq REG, REG 1208 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1209} // isCommutable 1210 1211// NOTE: These are order specific, we want the ri8 forms to be listed 1212// first so that they are slightly preferred to the ri forms. 1213 1214def ADD16ri8_DB : I<0, Pseudo, 1215 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1216 "", // orw/addw REG, imm8 1217 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1218def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1219 "", // orw/addw REG, imm 1220 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1221 1222def ADD32ri8_DB : I<0, Pseudo, 1223 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1224 "", // orl/addl REG, imm8 1225 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1226def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1227 "", // orl/addl REG, imm 1228 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1229 1230 1231def ADD64ri8_DB : I<0, Pseudo, 1232 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1233 "", // orq/addq REG, imm8 1234 [(set GR64:$dst, (or_is_add GR64:$src1, 1235 i64immSExt8:$src2))]>; 1236def ADD64ri32_DB : I<0, Pseudo, 1237 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1238 "", // orq/addq REG, imm 1239 [(set GR64:$dst, (or_is_add GR64:$src1, 1240 i64immSExt32:$src2))]>; 1241} 1242} // AddedComplexity 1243 1244 1245//===----------------------------------------------------------------------===// 1246// Some peepholes 1247//===----------------------------------------------------------------------===// 1248 1249// Odd encoding trick: -128 fits into an 8-bit immediate field while 1250// +128 doesn't, so in this special case use a sub instead of an add. 1251def : Pat<(add GR16:$src1, 128), 1252 (SUB16ri8 GR16:$src1, -128)>; 1253def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1254 (SUB16mi8 addr:$dst, -128)>; 1255 1256def : Pat<(add GR32:$src1, 128), 1257 (SUB32ri8 GR32:$src1, -128)>; 1258def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1259 (SUB32mi8 addr:$dst, -128)>; 1260 1261def : Pat<(add GR64:$src1, 128), 1262 (SUB64ri8 GR64:$src1, -128)>; 1263def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1264 (SUB64mi8 addr:$dst, -128)>; 1265 1266// The same trick applies for 32-bit immediate fields in 64-bit 1267// instructions. 1268def : Pat<(add GR64:$src1, 0x0000000080000000), 1269 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1270def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1271 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1272 1273// To avoid needing to materialize an immediate in a register, use a 32-bit and 1274// with implicit zero-extension instead of a 64-bit and if the immediate has at 1275// least 32 bits of leading zeros. If in addition the last 32 bits can be 1276// represented with a sign extension of a 8 bit constant, use that. 1277 1278def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1279 (SUBREG_TO_REG 1280 (i64 0), 1281 (AND32ri8 1282 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1283 (i32 (GetLo8XForm imm:$imm))), 1284 sub_32bit)>; 1285 1286def : Pat<(and GR64:$src, i64immZExt32:$imm), 1287 (SUBREG_TO_REG 1288 (i64 0), 1289 (AND32ri 1290 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1291 (i32 (GetLo32XForm imm:$imm))), 1292 sub_32bit)>; 1293 1294 1295// r & (2^16-1) ==> movz 1296def : Pat<(and GR32:$src1, 0xffff), 1297 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1298// r & (2^8-1) ==> movz 1299def : Pat<(and GR32:$src1, 0xff), 1300 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1301 GR32_ABCD)), 1302 sub_8bit))>, 1303 Requires<[In32BitMode]>; 1304// r & (2^8-1) ==> movz 1305def : Pat<(and GR16:$src1, 0xff), 1306 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1307 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1308 sub_16bit)>, 1309 Requires<[In32BitMode]>; 1310 1311// r & (2^32-1) ==> movz 1312def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1313 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1314// r & (2^16-1) ==> movz 1315def : Pat<(and GR64:$src, 0xffff), 1316 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>; 1317// r & (2^8-1) ==> movz 1318def : Pat<(and GR64:$src, 0xff), 1319 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>; 1320// r & (2^8-1) ==> movz 1321def : Pat<(and GR32:$src1, 0xff), 1322 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1323 Requires<[In64BitMode]>; 1324// r & (2^8-1) ==> movz 1325def : Pat<(and GR16:$src1, 0xff), 1326 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1327 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1328 Requires<[In64BitMode]>; 1329 1330 1331// sext_inreg patterns 1332def : Pat<(sext_inreg GR32:$src, i16), 1333 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1334def : Pat<(sext_inreg GR32:$src, i8), 1335 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1336 GR32_ABCD)), 1337 sub_8bit))>, 1338 Requires<[In32BitMode]>; 1339 1340def : Pat<(sext_inreg GR16:$src, i8), 1341 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1342 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1343 sub_16bit)>, 1344 Requires<[In32BitMode]>; 1345 1346def : Pat<(sext_inreg GR64:$src, i32), 1347 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1348def : Pat<(sext_inreg GR64:$src, i16), 1349 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1350def : Pat<(sext_inreg GR64:$src, i8), 1351 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1352def : Pat<(sext_inreg GR32:$src, i8), 1353 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1354 Requires<[In64BitMode]>; 1355def : Pat<(sext_inreg GR16:$src, i8), 1356 (EXTRACT_SUBREG (MOVSX32rr8 1357 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1358 Requires<[In64BitMode]>; 1359 1360// sext, sext_load, zext, zext_load 1361def: Pat<(i16 (sext GR8:$src)), 1362 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1363def: Pat<(sextloadi16i8 addr:$src), 1364 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1365def: Pat<(i16 (zext GR8:$src)), 1366 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1367def: Pat<(zextloadi16i8 addr:$src), 1368 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1369 1370// trunc patterns 1371def : Pat<(i16 (trunc GR32:$src)), 1372 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1373def : Pat<(i8 (trunc GR32:$src)), 1374 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1375 sub_8bit)>, 1376 Requires<[In32BitMode]>; 1377def : Pat<(i8 (trunc GR16:$src)), 1378 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1379 sub_8bit)>, 1380 Requires<[In32BitMode]>; 1381def : Pat<(i32 (trunc GR64:$src)), 1382 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1383def : Pat<(i16 (trunc GR64:$src)), 1384 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1385def : Pat<(i8 (trunc GR64:$src)), 1386 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1387def : Pat<(i8 (trunc GR32:$src)), 1388 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1389 Requires<[In64BitMode]>; 1390def : Pat<(i8 (trunc GR16:$src)), 1391 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1392 Requires<[In64BitMode]>; 1393 1394// h-register tricks 1395def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1396 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1397 sub_8bit_hi)>, 1398 Requires<[In32BitMode]>; 1399def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1400 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1401 sub_8bit_hi)>, 1402 Requires<[In32BitMode]>; 1403def : Pat<(srl GR16:$src, (i8 8)), 1404 (EXTRACT_SUBREG 1405 (MOVZX32rr8 1406 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1407 sub_8bit_hi)), 1408 sub_16bit)>, 1409 Requires<[In32BitMode]>; 1410def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1411 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1412 GR16_ABCD)), 1413 sub_8bit_hi))>, 1414 Requires<[In32BitMode]>; 1415def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1416 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1417 GR16_ABCD)), 1418 sub_8bit_hi))>, 1419 Requires<[In32BitMode]>; 1420def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1421 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1422 GR32_ABCD)), 1423 sub_8bit_hi))>, 1424 Requires<[In32BitMode]>; 1425def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1426 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1427 GR32_ABCD)), 1428 sub_8bit_hi))>, 1429 Requires<[In32BitMode]>; 1430 1431// h-register tricks. 1432// For now, be conservative on x86-64 and use an h-register extract only if the 1433// value is immediately zero-extended or stored, which are somewhat common 1434// cases. This uses a bunch of code to prevent a register requiring a REX prefix 1435// from being allocated in the same instruction as the h register, as there's 1436// currently no way to describe this requirement to the register allocator. 1437 1438// h-register extract and zero-extend. 1439def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1440 (SUBREG_TO_REG 1441 (i64 0), 1442 (MOVZX32_NOREXrr8 1443 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1444 sub_8bit_hi)), 1445 sub_32bit)>; 1446def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1447 (MOVZX32_NOREXrr8 1448 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1449 sub_8bit_hi))>, 1450 Requires<[In64BitMode]>; 1451def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1452 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1453 GR32_ABCD)), 1454 sub_8bit_hi))>, 1455 Requires<[In64BitMode]>; 1456def : Pat<(srl GR16:$src, (i8 8)), 1457 (EXTRACT_SUBREG 1458 (MOVZX32_NOREXrr8 1459 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1460 sub_8bit_hi)), 1461 sub_16bit)>, 1462 Requires<[In64BitMode]>; 1463def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1464 (MOVZX32_NOREXrr8 1465 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1466 sub_8bit_hi))>, 1467 Requires<[In64BitMode]>; 1468def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1469 (MOVZX32_NOREXrr8 1470 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1471 sub_8bit_hi))>, 1472 Requires<[In64BitMode]>; 1473def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1474 (SUBREG_TO_REG 1475 (i64 0), 1476 (MOVZX32_NOREXrr8 1477 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1478 sub_8bit_hi)), 1479 sub_32bit)>; 1480def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1481 (SUBREG_TO_REG 1482 (i64 0), 1483 (MOVZX32_NOREXrr8 1484 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1485 sub_8bit_hi)), 1486 sub_32bit)>; 1487 1488// h-register extract and store. 1489def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1490 (MOV8mr_NOREX 1491 addr:$dst, 1492 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1493 sub_8bit_hi))>; 1494def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1495 (MOV8mr_NOREX 1496 addr:$dst, 1497 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1498 sub_8bit_hi))>, 1499 Requires<[In64BitMode]>; 1500def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1501 (MOV8mr_NOREX 1502 addr:$dst, 1503 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1504 sub_8bit_hi))>, 1505 Requires<[In64BitMode]>; 1506 1507 1508// (shl x, 1) ==> (add x, x) 1509// Note that if x is undef (immediate or otherwise), we could theoretically 1510// end up with the two uses of x getting different values, producing a result 1511// where the least significant bit is not 0. However, the probability of this 1512// happening is considered low enough that this is officially not a 1513// "real problem". 1514def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1515def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1516def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1517def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1518 1519// Helper imms that check if a mask doesn't change significant shift bits. 1520def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>; 1521def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>; 1522 1523// (shl x (and y, 31)) ==> (shl x, y) 1524def : Pat<(shl GR8:$src1, (and CL, immShift32)), 1525 (SHL8rCL GR8:$src1)>; 1526def : Pat<(shl GR16:$src1, (and CL, immShift32)), 1527 (SHL16rCL GR16:$src1)>; 1528def : Pat<(shl GR32:$src1, (and CL, immShift32)), 1529 (SHL32rCL GR32:$src1)>; 1530def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1531 (SHL8mCL addr:$dst)>; 1532def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1533 (SHL16mCL addr:$dst)>; 1534def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1535 (SHL32mCL addr:$dst)>; 1536 1537def : Pat<(srl GR8:$src1, (and CL, immShift32)), 1538 (SHR8rCL GR8:$src1)>; 1539def : Pat<(srl GR16:$src1, (and CL, immShift32)), 1540 (SHR16rCL GR16:$src1)>; 1541def : Pat<(srl GR32:$src1, (and CL, immShift32)), 1542 (SHR32rCL GR32:$src1)>; 1543def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1544 (SHR8mCL addr:$dst)>; 1545def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1546 (SHR16mCL addr:$dst)>; 1547def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1548 (SHR32mCL addr:$dst)>; 1549 1550def : Pat<(sra GR8:$src1, (and CL, immShift32)), 1551 (SAR8rCL GR8:$src1)>; 1552def : Pat<(sra GR16:$src1, (and CL, immShift32)), 1553 (SAR16rCL GR16:$src1)>; 1554def : Pat<(sra GR32:$src1, (and CL, immShift32)), 1555 (SAR32rCL GR32:$src1)>; 1556def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1557 (SAR8mCL addr:$dst)>; 1558def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1559 (SAR16mCL addr:$dst)>; 1560def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1561 (SAR32mCL addr:$dst)>; 1562 1563// (shl x (and y, 63)) ==> (shl x, y) 1564def : Pat<(shl GR64:$src1, (and CL, immShift64)), 1565 (SHL64rCL GR64:$src1)>; 1566def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1567 (SHL64mCL addr:$dst)>; 1568 1569def : Pat<(srl GR64:$src1, (and CL, immShift64)), 1570 (SHR64rCL GR64:$src1)>; 1571def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1572 (SHR64mCL addr:$dst)>; 1573 1574def : Pat<(sra GR64:$src1, (and CL, immShift64)), 1575 (SAR64rCL GR64:$src1)>; 1576def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1577 (SAR64mCL addr:$dst)>; 1578 1579 1580// (anyext (setcc_carry)) -> (setcc_carry) 1581def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1582 (SETB_C16r)>; 1583def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1584 (SETB_C32r)>; 1585def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1586 (SETB_C32r)>; 1587 1588 1589 1590 1591//===----------------------------------------------------------------------===// 1592// EFLAGS-defining Patterns 1593//===----------------------------------------------------------------------===// 1594 1595// add reg, reg 1596def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1597def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1598def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1599 1600// add reg, mem 1601def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1602 (ADD8rm GR8:$src1, addr:$src2)>; 1603def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1604 (ADD16rm GR16:$src1, addr:$src2)>; 1605def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1606 (ADD32rm GR32:$src1, addr:$src2)>; 1607 1608// add reg, imm 1609def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1610def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1611def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1612def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1613 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1614def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1615 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1616 1617// sub reg, reg 1618def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1619def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1620def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1621 1622// sub reg, mem 1623def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1624 (SUB8rm GR8:$src1, addr:$src2)>; 1625def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1626 (SUB16rm GR16:$src1, addr:$src2)>; 1627def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1628 (SUB32rm GR32:$src1, addr:$src2)>; 1629 1630// sub reg, imm 1631def : Pat<(sub GR8:$src1, imm:$src2), 1632 (SUB8ri GR8:$src1, imm:$src2)>; 1633def : Pat<(sub GR16:$src1, imm:$src2), 1634 (SUB16ri GR16:$src1, imm:$src2)>; 1635def : Pat<(sub GR32:$src1, imm:$src2), 1636 (SUB32ri GR32:$src1, imm:$src2)>; 1637def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1638 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1639def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1640 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1641 1642// sub 0, reg 1643def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1644def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1645def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1646def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1647 1648// mul reg, reg 1649def : Pat<(mul GR16:$src1, GR16:$src2), 1650 (IMUL16rr GR16:$src1, GR16:$src2)>; 1651def : Pat<(mul GR32:$src1, GR32:$src2), 1652 (IMUL32rr GR32:$src1, GR32:$src2)>; 1653 1654// mul reg, mem 1655def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1656 (IMUL16rm GR16:$src1, addr:$src2)>; 1657def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1658 (IMUL32rm GR32:$src1, addr:$src2)>; 1659 1660// mul reg, imm 1661def : Pat<(mul GR16:$src1, imm:$src2), 1662 (IMUL16rri GR16:$src1, imm:$src2)>; 1663def : Pat<(mul GR32:$src1, imm:$src2), 1664 (IMUL32rri GR32:$src1, imm:$src2)>; 1665def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1666 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1667def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1668 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1669 1670// reg = mul mem, imm 1671def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1672 (IMUL16rmi addr:$src1, imm:$src2)>; 1673def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1674 (IMUL32rmi addr:$src1, imm:$src2)>; 1675def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1676 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1677def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1678 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1679 1680// Patterns for nodes that do not produce flags, for instructions that do. 1681 1682// addition 1683def : Pat<(add GR64:$src1, GR64:$src2), 1684 (ADD64rr GR64:$src1, GR64:$src2)>; 1685def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1686 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1687def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1688 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1689def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1690 (ADD64rm GR64:$src1, addr:$src2)>; 1691 1692// subtraction 1693def : Pat<(sub GR64:$src1, GR64:$src2), 1694 (SUB64rr GR64:$src1, GR64:$src2)>; 1695def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1696 (SUB64rm GR64:$src1, addr:$src2)>; 1697def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1698 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1699def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1700 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1701 1702// Multiply 1703def : Pat<(mul GR64:$src1, GR64:$src2), 1704 (IMUL64rr GR64:$src1, GR64:$src2)>; 1705def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1706 (IMUL64rm GR64:$src1, addr:$src2)>; 1707def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1708 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1709def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1710 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1711def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1712 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1713def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1714 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1715 1716// Increment reg. 1717def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>; 1718def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>; 1719def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1720def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>; 1721def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1722def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1723 1724// Decrement reg. 1725def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>; 1726def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>; 1727def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>; 1728def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>; 1729def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>; 1730def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1731 1732// or reg/reg. 1733def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1734def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1735def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1736def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1737 1738// or reg/mem 1739def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1740 (OR8rm GR8:$src1, addr:$src2)>; 1741def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1742 (OR16rm GR16:$src1, addr:$src2)>; 1743def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1744 (OR32rm GR32:$src1, addr:$src2)>; 1745def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1746 (OR64rm GR64:$src1, addr:$src2)>; 1747 1748// or reg/imm 1749def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1750def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1751def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1752def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1753 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1754def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1755 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1756def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1757 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1758def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1759 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1760 1761// xor reg/reg 1762def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1763def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1764def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1765def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1766 1767// xor reg/mem 1768def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1769 (XOR8rm GR8:$src1, addr:$src2)>; 1770def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1771 (XOR16rm GR16:$src1, addr:$src2)>; 1772def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1773 (XOR32rm GR32:$src1, addr:$src2)>; 1774def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1775 (XOR64rm GR64:$src1, addr:$src2)>; 1776 1777// xor reg/imm 1778def : Pat<(xor GR8:$src1, imm:$src2), 1779 (XOR8ri GR8:$src1, imm:$src2)>; 1780def : Pat<(xor GR16:$src1, imm:$src2), 1781 (XOR16ri GR16:$src1, imm:$src2)>; 1782def : Pat<(xor GR32:$src1, imm:$src2), 1783 (XOR32ri GR32:$src1, imm:$src2)>; 1784def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1785 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1786def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1787 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1788def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1789 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1790def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1791 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1792 1793// and reg/reg 1794def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1795def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1796def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1797def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1798 1799// and reg/mem 1800def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1801 (AND8rm GR8:$src1, addr:$src2)>; 1802def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1803 (AND16rm GR16:$src1, addr:$src2)>; 1804def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1805 (AND32rm GR32:$src1, addr:$src2)>; 1806def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1807 (AND64rm GR64:$src1, addr:$src2)>; 1808 1809// and reg/imm 1810def : Pat<(and GR8:$src1, imm:$src2), 1811 (AND8ri GR8:$src1, imm:$src2)>; 1812def : Pat<(and GR16:$src1, imm:$src2), 1813 (AND16ri GR16:$src1, imm:$src2)>; 1814def : Pat<(and GR32:$src1, imm:$src2), 1815 (AND32ri GR32:$src1, imm:$src2)>; 1816def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1817 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1818def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1819 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1820def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1821 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1822def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1823 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1824 1825// Bit scan instruction patterns to match explicit zero-undef behavior. 1826def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1827def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1828def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1829def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1830def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1831def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1832