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Searched refs:RecVec (Results 1 – 7 of 7) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.h30 typedef std::vector<Record*> RecVec; typedef
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
185 RecVec ItinDefList;
189 RecVec ItinRWDefs;
192 RecVec WriteResDefs;
193 RecVec ReadAdvanceDefs;
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DCodeGenSchedule.cpp140 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); in collectProcModels()
183 static void scanSchedRW(Record *RWDef, RecVec &RWDefs, in scanSchedRW()
190 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
196 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
199 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()
216 RecVec SWDefs, SRDefs; in collectSchedRW()
222 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
233 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); in collectSchedRW()
236 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
248 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); in collectSchedRW()
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DSetTheory.h65 typedef std::vector<Record*> RecVec; typedef
94 typedef std::map<Record*, RecVec> ExpandMap;
136 const RecVec *expand(Record *Set);
DSetTheory.cpp26 typedef SetTheory::RecVec RecVec; typedef
219 if (const RecVec *Result = ST.expand(Rec)) in apply()
273 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
296 const RecVec *SetTheory::expand(Record *Set) { in expand()
310 RecVec &EltVec = Expansions[Set]; in expand()
DSubtargetEmitter.cpp90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
639 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
791 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()
797 RecVec SubResources; in ExpandProcResources()
810 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources"); in ExpandProcResources()
893 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses"); in GenSchedClassTables()
946 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); in GenSchedClassTables()
990 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
DRegisterInfoEmitter.cpp1295 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
DCodeGenRegisters.cpp722 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()