| /external/qemu/target-i386/ |
| D | ops_sse_header.h | 21 #define Reg MMXReg macro
24 #define Reg XMMReg macro
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg)
42 DEF_HELPER_2(glue(psrad, SUFFIX), void, Reg, Reg)
43 DEF_HELPER_2(glue(pslld, SUFFIX), void, Reg, Reg)
44 DEF_HELPER_2(glue(psrlq, SUFFIX), void, Reg, Reg)
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| D | ops_sse.h | 22 #define Reg MMXReg macro
30 #define Reg XMMReg macro
39 void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s) in glue()
63 void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s) in glue()
84 void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s) in glue()
108 void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s) in glue()
128 void glue(helper_psrad, SUFFIX)(Reg *d, Reg *s) in glue()
145 void glue(helper_pslld, SUFFIX)(Reg *d, Reg *s) in glue()
165 void glue(helper_psrlq, SUFFIX)(Reg *d, Reg *s) in glue()
183 void glue(helper_psllq, SUFFIX)(Reg *d, Reg *s) in glue()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
61 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
75 Regs.push_back(Reg); in GetGroupRegs()
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
102 GroupNodeIndices[Reg] = idx; in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
160 unsigned Reg = *AI; in StartBlock() local
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| D | CriticalAntiDepBreaker.cpp | 66 unsigned Reg = *AI; in StartBlock() local
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
68 KillIndices[Reg] = BBSize; in StartBlock()
69 DefIndices[Reg] = ~0u; in StartBlock()
81 unsigned Reg = *AI; in StartBlock() local
82 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
83 KillIndices[Reg] = BBSize; in StartBlock()
84 DefIndices[Reg] = ~0u; in StartBlock()
100 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
101 if (KillIndices[Reg] != ~0u) { in Observe()
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| D | MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
41 VRegInfo[Reg].first = RC; in setRegClass()
45 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
48 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
56 setRegClass(Reg, NewRC); in constrainRegClass()
61 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { in recomputeRegClass() argument
63 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
71 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; in recomputeRegClass()
85 setRegClass(Reg, NewRC); in recomputeRegClass()
99 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
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| D | MachineInstrBundle.cpp | 133 unsigned Reg = MO.getReg(); in finalizeBundle() local
134 if (!Reg) in finalizeBundle()
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); in finalizeBundle()
137 if (LocalDefSet.count(Reg)) { in finalizeBundle()
141 KilledDefSet.insert(Reg); in finalizeBundle()
143 if (ExternUseSet.insert(Reg)) { in finalizeBundle()
144 ExternUses.push_back(Reg); in finalizeBundle()
146 UndefUseSet.insert(Reg); in finalizeBundle()
150 KilledUseSet.insert(Reg); in finalizeBundle()
156 unsigned Reg = MO.getReg(); in finalizeBundle() local
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| D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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| D | RegisterPressure.cpp | 49 void RegisterPressure::increase(unsigned Reg, const TargetRegisterInfo *TRI, in increase() argument
51 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in increase()
52 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in increase()
59 TRI->getRegUnitPressureSets(Reg), in increase()
60 TRI->getRegUnitWeight(Reg)); in increase()
65 void RegisterPressure::decrease(unsigned Reg, const TargetRegisterInfo *TRI, in decrease() argument
67 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in decrease()
68 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in decrease()
73 decreaseSetPressure(MaxSetPressure, TRI->getRegUnitPressureSets(Reg), in decrease()
74 TRI->getRegUnitWeight(Reg)); in decrease()
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| D | DeadMachineInstructionElim.cpp | 69 unsigned Reg = MO.getReg(); in isDead() local
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in isDead()
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) in isDead()
75 if (!MRI->use_nodbg_empty(Reg)) in isDead()
127 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
128 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in runOnMachineFunction()
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), in runOnMachineFunction()
155 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in runOnMachineFunction()
157 LivePhysRegs.reset(Reg); in runOnMachineFunction()
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| D | MachineLICM.cpp | 179 void AddToLiveIns(unsigned Reg);
201 unsigned Reg) const;
247 unsigned Reg, unsigned OpIdx,
433 unsigned Reg = MO.getReg(); in ProcessMI() local
434 if (!Reg) in ProcessMI()
436 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && in ProcessMI()
440 if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg))) in ProcessMI()
448 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in ProcessMI()
463 Def = Reg; in ProcessMI()
468 for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) { in ProcessMI()
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| D | RegisterScavenging.cpp | 33 void RegScavenger::setUsed(unsigned Reg) { in setUsed() argument
34 RegsAvailable.reset(Reg); in setUsed()
36 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in setUsed()
40 bool RegScavenger::isAliasUsed(unsigned Reg) const { in isAliasUsed()
41 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in isAliasUsed()
42 if (isUsed(*AI, *AI == Reg)) in isAliasUsed()
105 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { in addRegWithSubRegs() argument
106 BV.set(Reg); in addRegWithSubRegs()
107 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in addRegWithSubRegs()
147 unsigned Reg = MO.getReg(); in forward() local
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| D | RegAllocFast.cpp | 702 unsigned Reg = MO.getReg(); in handleThroughOperands() local
703 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in handleThroughOperands()
706 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
707 if (ThroughRegs.insert(Reg)) in handleThroughOperands()
708 DEBUG(dbgs() << ' ' << PrintReg(Reg)); in handleThroughOperands()
718 unsigned Reg = MO.getReg(); in handleThroughOperands() local
719 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; in handleThroughOperands()
720 markRegUsedInInstr(Reg); in handleThroughOperands()
721 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in handleThroughOperands()
732 unsigned Reg = MO.getReg(); in handleThroughOperands() local
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| D | MachineSink.cpp | 89 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
94 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
156 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, in AllUsesDominatedByBlock() argument
161 assert(TargetRegisterInfo::isVirtualRegister(Reg) && in AllUsesDominatedByBlock()
165 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
185 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); in AllUsesDominatedByBlock()
199 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); in AllUsesDominatedByBlock()
312 unsigned Reg = MO.getReg(); in isWorthBreakingCriticalEdge() local
313 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) in isWorthBreakingCriticalEdge()
315 if (MRI->hasOneNonDBGUse(Reg)) in isWorthBreakingCriticalEdge()
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| D | MachineVerifier.cpp | 91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { in addRegWithSubRegs()
92 RV.push_back(Reg); in addRegWithSubRegs()
93 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in addRegWithSubRegs()
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in addRegWithSubRegs()
129 bool addPassed(unsigned Reg) { in addPassed()
130 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addPassed()
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) in addPassed()
134 return vregsPassed.insert(Reg).second; in addPassed()
148 bool addRequired(unsigned Reg) { in addRequired()
149 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addRequired()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConvLower.h | 74 bool isAllocated(unsigned Reg) const { in isAllocated() argument
75 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
121 unsigned AllocateReg(unsigned Reg) { in AllocateReg() argument
122 if (isAllocated(Reg)) return 0; in AllocateReg()
123 MarkAllocated(Reg); in AllocateReg()
124 return Reg; in AllocateReg()
128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() argument
129 if (isAllocated(Reg)) return 0; in AllocateReg()
130 MarkAllocated(Reg); in AllocateReg()
132 return Reg; in AllocateReg()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
90 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
100 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
106 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 77 return MO->Contents.Reg.Next; in getNextOperandForReg()
269 MachineInstr *getVRegDef(unsigned Reg) const;
274 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
280 void clearKillFlags(unsigned Reg) const;
297 const TargetRegisterClass *getRegClass(unsigned Reg) const { in getRegClass() argument
298 return VRegInfo[Reg].first; in getRegClass()
303 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
312 const TargetRegisterClass *constrainRegClass(unsigned Reg,
324 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
340 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument
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| D | LiveVariables.h | 112 unsigned Reg,
155 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
160 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
161 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
167 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
172 MachineInstr *FindLastPartialDef(unsigned Reg,
186 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
193 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
283 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { in isLiveIn() argument
284 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn()
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| D | RegisterPressure.h | 43 void increase(unsigned Reg, const TargetRegisterInfo *TRI,
50 void decrease(unsigned Reg, const TargetRegisterInfo *TRI,
134 bool contains(unsigned Reg) { in contains()
135 if (TargetRegisterInfo::isVirtualRegister(Reg)) in contains()
136 return VirtRegs.count(Reg); in contains()
137 return PhysRegs.count(Reg); in contains()
140 bool insert(unsigned Reg) { in insert()
141 if (TargetRegisterInfo::isVirtualRegister(Reg)) in insert()
142 return VirtRegs.insert(Reg).second; in insert()
143 return PhysRegs.insert(Reg).second; in insert()
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| D | LiveIntervalAnalysis.h | 105 LiveInterval &getInterval(unsigned Reg) { in getInterval() argument
106 LiveInterval *LI = VirtRegIntervals[Reg]; in getInterval()
111 const LiveInterval &getInterval(unsigned Reg) const { in getInterval() argument
112 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
115 bool hasInterval(unsigned Reg) const { in hasInterval() argument
116 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; in hasInterval()
120 LiveInterval &getOrCreateInterval(unsigned Reg) { in getOrCreateInterval() argument
121 if (!hasInterval(Reg)) { in getOrCreateInterval()
122 VirtRegIntervals.grow(Reg); in getOrCreateInterval()
123 VirtRegIntervals[Reg] = createInterval(Reg); in getOrCreateInterval()
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| D | CallingConvLower.h | 191 bool isAllocated(unsigned Reg) const { in isAllocated() argument
192 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
243 unsigned AllocateReg(unsigned Reg) { in AllocateReg() argument
244 if (isAllocated(Reg)) return 0; in AllocateReg()
245 MarkAllocated(Reg); in AllocateReg()
246 return Reg; in AllocateReg()
250 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() argument
251 if (isAllocated(Reg)) return 0; in AllocateReg()
252 MarkAllocated(Reg); in AllocateReg()
254 return Reg; in AllocateReg()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 76 bool contains(unsigned Reg) const { in contains() argument
77 return MC->contains(Reg); in contains()
258 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
259 return int(Reg) >= (1 << 30); in isStackSlot()
264 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
265 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
266 return int(Reg - (1u << 30)); in stackSlot2Index()
278 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
279 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
280 return int(Reg) > 0; in isPhysicalRegister()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 71 bool contains(unsigned Reg) const { in contains() argument
72 unsigned InByte = Reg % 8; in contains()
73 unsigned Byte = Reg / 8; in contains()
323 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
327 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
426 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { in MCSubRegIterator() argument
427 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); in MCSubRegIterator()
435 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { in MCSuperRegIterator() argument
436 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); in MCSuperRegIterator()
445 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, in MCRegAliasIterator() argument
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUIndirectAddressing.cpp | 37 bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const;
166 unsigned Reg = *LJ; in runOnMachineFunction() local
167 if (RegisterAddressMap.find(Reg) == RegisterAddressMap.end()) { in runOnMachineFunction()
171 if (RegisterAddressMap[Reg] == Address) { in runOnMachineFunction()
172 PhiRegisters.push_back(Reg); in runOnMachineFunction()
194 unsigned Reg = *RI; in runOnMachineFunction() local
195 MachineInstr *DefInst = MRI.getVRegDef(Reg); in runOnMachineFunction()
198 Phi.addReg(Reg); in runOnMachineFunction()
200 MBB.removeLiveIn(Reg); in runOnMachineFunction()
223 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers) in getMatchingSuperReg()
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg() argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg()
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex() argument
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex()
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
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