| /external/llvm/test/CodeGen/Hexagon/ |
| D | newvaluejump2.ll | 9 %Reg2 = alloca i8, align 1
10 %0 = load i8* %Reg2, align 1
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg2, bool isKill2) { in addRegReg() argument
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| D | X86FastISel.cpp | 1494 unsigned Reg2 = getRegForValue(Op2); in X86VisitIntrinsicCall() local
1496 if (Reg1 == 0 || Reg2 == 0) in X86VisitIntrinsicCall()
1512 .addReg(Reg1).addReg(Reg2); in X86VisitIntrinsicCall()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 137 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() local
148 Reg0 = Reg2; in commuteInstruction()
150 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
168 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
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| D | AggressiveAntiDepBreaker.h | 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | StrongPHIElimination.cpp | 438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { in unionRegs() argument
440 Node *Node2 = RegNodeMap[Reg2]->getLeader(); in unionRegs()
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| D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
86 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
81 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.h | 111 unsigned Reg1, unsigned Reg2) const;
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| D | Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
284 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| D | MipsISelLowering.cpp | 2486 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32() local
2487 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) in CC_MipsO32()
2914 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), in LowerFormalArguments() local
2916 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 155 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction() local
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction()
179 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
186 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
188 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 620 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
623 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
625 if (Reg0 != Reg2) { in ReduceTo2Addr()
653 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
654 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| D | A15SDOptimizer.cpp | 90 unsigned Reg1, unsigned Reg2);
470 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
478 .addReg(Reg2) in createRegSequence()
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| D | ARMFastISel.cpp | 2704 unsigned Reg2 = 0; in SelectShift() local
2706 Reg2 = getRegForValue(Src2Value); in SelectShift()
2707 if (Reg2 == 0) return false; in SelectShift()
2720 MIB.addReg(Reg2); in SelectShift()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
82 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 976 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local
980 Streamer.AddComment(Twine("Reg2 ") + Twine(Reg2)); in EmitCFIInstruction()
984 Streamer.EmitULEB128IntValue(Reg2); in EmitCFIInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1160 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
1162 if (Reg1 == Reg2) in computeComposites()
1164 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1171 if (Reg2 == Reg3) in computeComposites()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5217 unsigned Reg2 = Op2->getReg(); in ParseInstruction() local
5219 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction()
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