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Searched refs:SELECT_CC (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
95 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
315 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
563 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
609 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
640 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
642 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
649 return DAG.getNode(ISD::SELECT_CC, in LowerSELECT()
1004 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
[all …]
DSIISelLowering.cpp69 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SITargetLowering()
70 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SITargetLowering()
72 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in SITargetLowering()
73 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
249 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
379 case ISD::SELECT_CC: { in PerformDAGCombine()
DAMDILISelLowering.cpp158 setOperationAction(ISD::SELECT_CC, VT, Expand); in InitAMDILLowering()
268 case ISD::SELECT_CC: in computeMaskedBitsForTargetNode()
/external/llvm/test/CodeGen/ARM/
D2010-04-09-NeonSelect.ll2 ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values.
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td343 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
348 "# SELECT_CC PSEUDO!",
1165 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1168 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1171 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1173 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1175 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1177 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1179 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
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DXCoreISelLowering.cpp88 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in XCoreTargetLowering()
95 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in XCoreTargetLowering()
181 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1291 assert((MI->getOpcode() == XCore::SELECT_CC) && in EmitInstrWithCustomInserter()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp101 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
102 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
103 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
229 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
775 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC"; in getTargetNodeName()
2125 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), in LowerSELECT_CC()
2137 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, in LowerSELECT_CC()
2143 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), in LowerSELECT_CC()
2168 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), in LowerSELECT()
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DAArch64ISelLowering.h71 SELECT_CC, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h343 SELECT_CC, enumerator
DSelectionDAG.h625 return getNode(ISD::SELECT_CC, DL, True.getValueType(),
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
197 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
870 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); in LowerSETCC()
893 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); in LowerSELECT_CC()
1031 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
DMSP430ISelLowering.h62 SELECT_CC, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp97 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
536 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), in SoftenFloatRes_SELECT_CC()
615 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
790 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
857 Lo = DAG.getNode(ISD::SELECT_CC, dl, Lo.getValueType(), Tmp, Hi, Lo, in ExpandFloatRes_FABS()
1208 Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT), in ExpandFloatRes_XINT_TO_FP()
1246 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
1362 return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp, in ExpandFloatOp_FP_TO_UINT()
DLegalizeTypesGeneric.cpp514 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
516 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
DSelectionDAGDumper.cpp191 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
DLegalizeVectorTypes.cpp63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; in ScalarizeVectorResult()
291 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), in ScalarizeVecRes_SELECT_CC()
498 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
1371 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; in WidenVectorResult()
2082 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), in WidenVecRes_SELECT_CC()
DDAGCombiner.cpp553 if (N.getOpcode() == ISD::SELECT_CC && in isSetCCEquivalent()
1130 case ISD::SELECT_CC: return visitSELECT_CC(N); in visit()
3421 case ISD::SELECT_CC: in visitXOR()
4156 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && in visitSELECT()
4157 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) in visitSELECT()
4158 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, in visitSELECT()
4193 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), in visitSELECT_CC()
6381 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { in visitSINT_TO_FP()
6391 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); in visitSINT_TO_FP()
6404 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); in visitSINT_TO_FP()
[all …]
DLegalizeIntegerTypes.cpp69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; in PromoteIntegerResult()
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), in PromoteIntRes_SELECT_CC()
785 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; in PromoteIntegerOperand()
1099 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandIntegerResult()
2475 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; in ExpandIntegerOperand()
DLegalizeDAG.cpp1185 case ISD::SELECT_CC: in LegalizeOp()
1188 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : in LegalizeOp()
1196 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3645 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3651 case ISD::SELECT_CC: { in ExpandNode()
3664 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, in ExpandNode()
DLegalizeVectorOps.cpp220 case ISD::SELECT_CC: in LegalizeOp()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1337 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in HexagonTargetLowering()
1338 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in HexagonTargetLowering()
1348 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in HexagonTargetLowering()
1349 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in HexagonTargetLowering()
1350 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in HexagonTargetLowering()
1360 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in HexagonTargetLowering()
1538 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/MBlaze/
DMBlazeISelLowering.cpp131 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in MBlazeTargetLowering()
145 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32); in MBlazeTargetLowering()
207 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
DMBlazeInstrInfo.td612 "; SELECT_CC PSEUDO!",
848 // SELECT_CC
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp748 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
749 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
750 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1156 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in MipsTargetLowering()
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in MipsTargetLowering()
284 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in MipsTargetLowering()
906 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); in LowerOperation()

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