1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "SparcISelLowering.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcTargetMachine.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Module.h"
28 #include "llvm/Support/ErrorHandling.h"
29 using namespace llvm;
30
31
32 //===----------------------------------------------------------------------===//
33 // Calling Convention Implementation
34 //===----------------------------------------------------------------------===//
35
CC_Sparc_Assign_SRet(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)36 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
37 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
38 ISD::ArgFlagsTy &ArgFlags, CCState &State)
39 {
40 assert (ArgFlags.isSRet());
41
42 //Assign SRet argument
43 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
44 0,
45 LocVT, LocInfo));
46 return true;
47 }
48
CC_Sparc_Assign_f64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)49 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
50 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags, CCState &State)
52 {
53 static const uint16_t RegList[] = {
54 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
55 };
56 //Try to get first reg
57 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
58 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
59 } else {
60 //Assign whole thing in stack
61 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
62 State.AllocateStack(8,4),
63 LocVT, LocInfo));
64 return true;
65 }
66
67 //Try to get second reg
68 if (unsigned Reg = State.AllocateReg(RegList, 6))
69 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
70 else
71 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
72 State.AllocateStack(4,4),
73 LocVT, LocInfo));
74 return true;
75 }
76
77 #include "SparcGenCallingConv.inc"
78
79 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,DebugLoc dl,SelectionDAG & DAG) const80 SparcTargetLowering::LowerReturn(SDValue Chain,
81 CallingConv::ID CallConv, bool isVarArg,
82 const SmallVectorImpl<ISD::OutputArg> &Outs,
83 const SmallVectorImpl<SDValue> &OutVals,
84 DebugLoc dl, SelectionDAG &DAG) const {
85
86 MachineFunction &MF = DAG.getMachineFunction();
87
88 // CCValAssign - represent the assignment of the return value to locations.
89 SmallVector<CCValAssign, 16> RVLocs;
90
91 // CCState - Info about the registers and stack slot.
92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
93 DAG.getTarget(), RVLocs, *DAG.getContext());
94
95 // Analize return values.
96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
97
98 SDValue Flag;
99 SmallVector<SDValue, 4> RetOps(1, Chain);
100 // Make room for the return address offset.
101 RetOps.push_back(SDValue());
102
103 // Copy the result values into the output registers.
104 for (unsigned i = 0; i != RVLocs.size(); ++i) {
105 CCValAssign &VA = RVLocs[i];
106 assert(VA.isRegLoc() && "Can only return in registers!");
107
108 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
109 OutVals[i], Flag);
110
111 // Guarantee that all emitted copies are stuck together with flags.
112 Flag = Chain.getValue(1);
113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
114 }
115
116 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot
117 // If the function returns a struct, copy the SRetReturnReg to I0
118 if (MF.getFunction()->hasStructRetAttr()) {
119 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
120 unsigned Reg = SFI->getSRetReturnReg();
121 if (!Reg)
122 llvm_unreachable("sret virtual register not created in the entry block");
123 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
124 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag);
125 Flag = Chain.getValue(1);
126 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
127 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
128 }
129
130 RetOps[0] = Chain; // Update chain.
131 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
132
133 // Add the flag if we have it.
134 if (Flag.getNode())
135 RetOps.push_back(Flag);
136
137 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other,
138 &RetOps[0], RetOps.size());
139 }
140
141 /// LowerFormalArguments - V8 uses a very simple ABI, where all values are
142 /// passed in either one or two GPRs, including FP values. TODO: we should
143 /// pass FP values in FP registers for fastcc functions.
144 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const145 SparcTargetLowering::LowerFormalArguments(SDValue Chain,
146 CallingConv::ID CallConv, bool isVarArg,
147 const SmallVectorImpl<ISD::InputArg>
148 &Ins,
149 DebugLoc dl, SelectionDAG &DAG,
150 SmallVectorImpl<SDValue> &InVals)
151 const {
152
153 MachineFunction &MF = DAG.getMachineFunction();
154 MachineRegisterInfo &RegInfo = MF.getRegInfo();
155 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
156
157 // Assign locations to all of the incoming arguments.
158 SmallVector<CCValAssign, 16> ArgLocs;
159 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
160 getTargetMachine(), ArgLocs, *DAG.getContext());
161 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
162
163 const unsigned StackOffset = 92;
164
165 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
166 CCValAssign &VA = ArgLocs[i];
167
168 if (i == 0 && Ins[i].Flags.isSRet()) {
169 //Get SRet from [%fp+64]
170 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
171 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
172 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
173 MachinePointerInfo(),
174 false, false, false, 0);
175 InVals.push_back(Arg);
176 continue;
177 }
178
179 if (VA.isRegLoc()) {
180 if (VA.needsCustom()) {
181 assert(VA.getLocVT() == MVT::f64);
182 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
183 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
184 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
185
186 assert(i+1 < e);
187 CCValAssign &NextVA = ArgLocs[++i];
188
189 SDValue LoVal;
190 if (NextVA.isMemLoc()) {
191 int FrameIdx = MF.getFrameInfo()->
192 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
193 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
194 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
195 MachinePointerInfo(),
196 false, false, false, 0);
197 } else {
198 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
199 &SP::IntRegsRegClass);
200 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
201 }
202 SDValue WholeValue =
203 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
204 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
205 InVals.push_back(WholeValue);
206 continue;
207 }
208 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
209 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
210 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
211 if (VA.getLocVT() == MVT::f32)
212 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
213 else if (VA.getLocVT() != MVT::i32) {
214 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
215 DAG.getValueType(VA.getLocVT()));
216 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
217 }
218 InVals.push_back(Arg);
219 continue;
220 }
221
222 assert(VA.isMemLoc());
223
224 unsigned Offset = VA.getLocMemOffset()+StackOffset;
225
226 if (VA.needsCustom()) {
227 assert(VA.getValVT() == MVT::f64);
228 //If it is double-word aligned, just load.
229 if (Offset % 8 == 0) {
230 int FI = MF.getFrameInfo()->CreateFixedObject(8,
231 Offset,
232 true);
233 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
234 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
235 MachinePointerInfo(),
236 false,false, false, 0);
237 InVals.push_back(Load);
238 continue;
239 }
240
241 int FI = MF.getFrameInfo()->CreateFixedObject(4,
242 Offset,
243 true);
244 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
245 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
246 MachinePointerInfo(),
247 false, false, false, 0);
248 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
249 Offset+4,
250 true);
251 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
252
253 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
254 MachinePointerInfo(),
255 false, false, false, 0);
256
257 SDValue WholeValue =
258 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
259 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
260 InVals.push_back(WholeValue);
261 continue;
262 }
263
264 int FI = MF.getFrameInfo()->CreateFixedObject(4,
265 Offset,
266 true);
267 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
268 SDValue Load ;
269 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
270 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
271 MachinePointerInfo(),
272 false, false, false, 0);
273 } else {
274 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
275 // Sparc is big endian, so add an offset based on the ObjectVT.
276 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
277 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
278 DAG.getConstant(Offset, MVT::i32));
279 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
280 MachinePointerInfo(),
281 VA.getValVT(), false, false,0);
282 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
283 }
284 InVals.push_back(Load);
285 }
286
287 if (MF.getFunction()->hasStructRetAttr()) {
288 //Copy the SRet Argument to SRetReturnReg
289 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
290 unsigned Reg = SFI->getSRetReturnReg();
291 if (!Reg) {
292 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
293 SFI->setSRetReturnReg(Reg);
294 }
295 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
296 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
297 }
298
299 // Store remaining ArgRegs to the stack if this is a varargs function.
300 if (isVarArg) {
301 static const uint16_t ArgRegs[] = {
302 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
303 };
304 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
305 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
306 unsigned ArgOffset = CCInfo.getNextStackOffset();
307 if (NumAllocated == 6)
308 ArgOffset += StackOffset;
309 else {
310 assert(!ArgOffset);
311 ArgOffset = 68+4*NumAllocated;
312 }
313
314 // Remember the vararg offset for the va_start implementation.
315 FuncInfo->setVarArgsFrameOffset(ArgOffset);
316
317 std::vector<SDValue> OutChains;
318
319 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
320 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
321 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
322 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
323
324 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
325 true);
326 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
327
328 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
329 MachinePointerInfo(),
330 false, false, 0));
331 ArgOffset += 4;
332 }
333
334 if (!OutChains.empty()) {
335 OutChains.push_back(Chain);
336 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
337 &OutChains[0], OutChains.size());
338 }
339 }
340
341 return Chain;
342 }
343
344 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const345 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
346 SmallVectorImpl<SDValue> &InVals) const {
347 SelectionDAG &DAG = CLI.DAG;
348 DebugLoc &dl = CLI.DL;
349 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
350 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
351 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
352 SDValue Chain = CLI.Chain;
353 SDValue Callee = CLI.Callee;
354 bool &isTailCall = CLI.IsTailCall;
355 CallingConv::ID CallConv = CLI.CallConv;
356 bool isVarArg = CLI.IsVarArg;
357
358 // Sparc target does not yet support tail call optimization.
359 isTailCall = false;
360
361 // Analyze operands of the call, assigning locations to each operand.
362 SmallVector<CCValAssign, 16> ArgLocs;
363 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
364 DAG.getTarget(), ArgLocs, *DAG.getContext());
365 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
366
367 // Get the size of the outgoing arguments stack space requirement.
368 unsigned ArgsSize = CCInfo.getNextStackOffset();
369
370 // Keep stack frames 8-byte aligned.
371 ArgsSize = (ArgsSize+7) & ~7;
372
373 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
374
375 //Create local copies for byval args.
376 SmallVector<SDValue, 8> ByValArgs;
377 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
378 ISD::ArgFlagsTy Flags = Outs[i].Flags;
379 if (!Flags.isByVal())
380 continue;
381
382 SDValue Arg = OutVals[i];
383 unsigned Size = Flags.getByValSize();
384 unsigned Align = Flags.getByValAlign();
385
386 int FI = MFI->CreateStackObject(Size, Align, false);
387 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
388 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
389
390 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
391 false, //isVolatile,
392 (Size <= 32), //AlwaysInline if size <= 32
393 MachinePointerInfo(), MachinePointerInfo());
394 ByValArgs.push_back(FIPtr);
395 }
396
397 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
398
399 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
400 SmallVector<SDValue, 8> MemOpChains;
401
402 const unsigned StackOffset = 92;
403 bool hasStructRetAttr = false;
404 // Walk the register/memloc assignments, inserting copies/loads.
405 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
406 i != e;
407 ++i, ++realArgIdx) {
408 CCValAssign &VA = ArgLocs[i];
409 SDValue Arg = OutVals[realArgIdx];
410
411 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
412
413 //Use local copy if it is a byval arg.
414 if (Flags.isByVal())
415 Arg = ByValArgs[byvalArgIdx++];
416
417 // Promote the value if needed.
418 switch (VA.getLocInfo()) {
419 default: llvm_unreachable("Unknown loc info!");
420 case CCValAssign::Full: break;
421 case CCValAssign::SExt:
422 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
423 break;
424 case CCValAssign::ZExt:
425 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
426 break;
427 case CCValAssign::AExt:
428 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
429 break;
430 case CCValAssign::BCvt:
431 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
432 break;
433 }
434
435 if (Flags.isSRet()) {
436 assert(VA.needsCustom());
437 // store SRet argument in %sp+64
438 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
439 SDValue PtrOff = DAG.getIntPtrConstant(64);
440 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
441 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
442 MachinePointerInfo(),
443 false, false, 0));
444 hasStructRetAttr = true;
445 continue;
446 }
447
448 if (VA.needsCustom()) {
449 assert(VA.getLocVT() == MVT::f64);
450
451 if (VA.isMemLoc()) {
452 unsigned Offset = VA.getLocMemOffset() + StackOffset;
453 //if it is double-word aligned, just store.
454 if (Offset % 8 == 0) {
455 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
456 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
457 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
458 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
459 MachinePointerInfo(),
460 false, false, 0));
461 continue;
462 }
463 }
464
465 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
466 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
467 Arg, StackPtr, MachinePointerInfo(),
468 false, false, 0);
469 // Sparc is big-endian, so the high part comes first.
470 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
471 MachinePointerInfo(), false, false, false, 0);
472 // Increment the pointer to the other half.
473 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
474 DAG.getIntPtrConstant(4));
475 // Load the low part.
476 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
477 MachinePointerInfo(), false, false, false, 0);
478
479 if (VA.isRegLoc()) {
480 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
481 assert(i+1 != e);
482 CCValAssign &NextVA = ArgLocs[++i];
483 if (NextVA.isRegLoc()) {
484 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
485 } else {
486 //Store the low part in stack.
487 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
488 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
489 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
490 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
491 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
492 MachinePointerInfo(),
493 false, false, 0));
494 }
495 } else {
496 unsigned Offset = VA.getLocMemOffset() + StackOffset;
497 // Store the high part.
498 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
499 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
500 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
501 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
502 MachinePointerInfo(),
503 false, false, 0));
504 // Store the low part.
505 PtrOff = DAG.getIntPtrConstant(Offset+4);
506 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
507 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
508 MachinePointerInfo(),
509 false, false, 0));
510 }
511 continue;
512 }
513
514 // Arguments that can be passed on register must be kept at
515 // RegsToPass vector
516 if (VA.isRegLoc()) {
517 if (VA.getLocVT() != MVT::f32) {
518 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
519 continue;
520 }
521 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
522 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
523 continue;
524 }
525
526 assert(VA.isMemLoc());
527
528 // Create a store off the stack pointer for this argument.
529 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
530 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
531 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
532 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
533 MachinePointerInfo(),
534 false, false, 0));
535 }
536
537
538 // Emit all stores, make sure the occur before any copies into physregs.
539 if (!MemOpChains.empty())
540 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
541 &MemOpChains[0], MemOpChains.size());
542
543 // Build a sequence of copy-to-reg nodes chained together with token
544 // chain and flag operands which copy the outgoing args into registers.
545 // The InFlag in necessary since all emitted instructions must be
546 // stuck together.
547 SDValue InFlag;
548 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
549 unsigned Reg = RegsToPass[i].first;
550 // Remap I0->I7 -> O0->O7.
551 if (Reg >= SP::I0 && Reg <= SP::I7)
552 Reg = Reg-SP::I0+SP::O0;
553
554 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
555 InFlag = Chain.getValue(1);
556 }
557
558 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
559
560 // If the callee is a GlobalAddress node (quite common, every direct call is)
561 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
562 // Likewise ExternalSymbol -> TargetExternalSymbol.
563 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
564 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
565 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
566 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
567
568 // Returns a chain & a flag for retval copy to use
569 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
570 SmallVector<SDValue, 8> Ops;
571 Ops.push_back(Chain);
572 Ops.push_back(Callee);
573 if (hasStructRetAttr)
574 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
575 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
576 unsigned Reg = RegsToPass[i].first;
577 if (Reg >= SP::I0 && Reg <= SP::I7)
578 Reg = Reg-SP::I0+SP::O0;
579
580 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
581 }
582 if (InFlag.getNode())
583 Ops.push_back(InFlag);
584
585 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
586 InFlag = Chain.getValue(1);
587
588 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
589 DAG.getIntPtrConstant(0, true), InFlag);
590 InFlag = Chain.getValue(1);
591
592 // Assign locations to each value returned by this call.
593 SmallVector<CCValAssign, 16> RVLocs;
594 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
595 DAG.getTarget(), RVLocs, *DAG.getContext());
596
597 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
598
599 // Copy all of the result registers out of their specified physreg.
600 for (unsigned i = 0; i != RVLocs.size(); ++i) {
601 unsigned Reg = RVLocs[i].getLocReg();
602
603 // Remap I0->I7 -> O0->O7.
604 if (Reg >= SP::I0 && Reg <= SP::I7)
605 Reg = Reg-SP::I0+SP::O0;
606
607 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
608 RVLocs[i].getValVT(), InFlag).getValue(1);
609 InFlag = Chain.getValue(2);
610 InVals.push_back(Chain.getValue(0));
611 }
612
613 return Chain;
614 }
615
616 unsigned
getSRetArgSize(SelectionDAG & DAG,SDValue Callee) const617 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
618 {
619 const Function *CalleeFn = 0;
620 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
621 CalleeFn = dyn_cast<Function>(G->getGlobal());
622 } else if (ExternalSymbolSDNode *E =
623 dyn_cast<ExternalSymbolSDNode>(Callee)) {
624 const Function *Fn = DAG.getMachineFunction().getFunction();
625 const Module *M = Fn->getParent();
626 CalleeFn = M->getFunction(E->getSymbol());
627 }
628
629 if (!CalleeFn)
630 return 0;
631
632 assert(CalleeFn->hasStructRetAttr() &&
633 "Callee does not have the StructRet attribute.");
634
635 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
636 Type *ElementTy = Ty->getElementType();
637 return getDataLayout()->getTypeAllocSize(ElementTy);
638 }
639
640 //===----------------------------------------------------------------------===//
641 // TargetLowering Implementation
642 //===----------------------------------------------------------------------===//
643
644 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
645 /// condition.
IntCondCCodeToICC(ISD::CondCode CC)646 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
647 switch (CC) {
648 default: llvm_unreachable("Unknown integer condition code!");
649 case ISD::SETEQ: return SPCC::ICC_E;
650 case ISD::SETNE: return SPCC::ICC_NE;
651 case ISD::SETLT: return SPCC::ICC_L;
652 case ISD::SETGT: return SPCC::ICC_G;
653 case ISD::SETLE: return SPCC::ICC_LE;
654 case ISD::SETGE: return SPCC::ICC_GE;
655 case ISD::SETULT: return SPCC::ICC_CS;
656 case ISD::SETULE: return SPCC::ICC_LEU;
657 case ISD::SETUGT: return SPCC::ICC_GU;
658 case ISD::SETUGE: return SPCC::ICC_CC;
659 }
660 }
661
662 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
663 /// FCC condition.
FPCondCCodeToFCC(ISD::CondCode CC)664 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
665 switch (CC) {
666 default: llvm_unreachable("Unknown fp condition code!");
667 case ISD::SETEQ:
668 case ISD::SETOEQ: return SPCC::FCC_E;
669 case ISD::SETNE:
670 case ISD::SETUNE: return SPCC::FCC_NE;
671 case ISD::SETLT:
672 case ISD::SETOLT: return SPCC::FCC_L;
673 case ISD::SETGT:
674 case ISD::SETOGT: return SPCC::FCC_G;
675 case ISD::SETLE:
676 case ISD::SETOLE: return SPCC::FCC_LE;
677 case ISD::SETGE:
678 case ISD::SETOGE: return SPCC::FCC_GE;
679 case ISD::SETULT: return SPCC::FCC_UL;
680 case ISD::SETULE: return SPCC::FCC_ULE;
681 case ISD::SETUGT: return SPCC::FCC_UG;
682 case ISD::SETUGE: return SPCC::FCC_UGE;
683 case ISD::SETUO: return SPCC::FCC_U;
684 case ISD::SETO: return SPCC::FCC_O;
685 case ISD::SETONE: return SPCC::FCC_LG;
686 case ISD::SETUEQ: return SPCC::FCC_UE;
687 }
688 }
689
SparcTargetLowering(TargetMachine & TM)690 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
691 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
692
693 // Set up the register classes.
694 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
695 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
696 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
697
698 // Turn FP extload into load/fextend
699 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
700 // Sparc doesn't have i1 sign extending load
701 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
702 // Turn FP truncstore into trunc + store.
703 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
704
705 // Custom legalize GlobalAddress nodes into LO/HI parts.
706 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
707 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
708 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
709
710 // Sparc doesn't have sext_inreg, replace them with shl/sra
711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
713 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
714
715 // Sparc has no REM or DIVREM operations.
716 setOperationAction(ISD::UREM, MVT::i32, Expand);
717 setOperationAction(ISD::SREM, MVT::i32, Expand);
718 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
719 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
720
721 // Custom expand fp<->sint
722 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
723 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
724
725 // Expand fp<->uint
726 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
727 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
728
729 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
730 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
731
732 // Sparc has no select or setcc: expand to SELECT_CC.
733 setOperationAction(ISD::SELECT, MVT::i32, Expand);
734 setOperationAction(ISD::SELECT, MVT::f32, Expand);
735 setOperationAction(ISD::SELECT, MVT::f64, Expand);
736 setOperationAction(ISD::SETCC, MVT::i32, Expand);
737 setOperationAction(ISD::SETCC, MVT::f32, Expand);
738 setOperationAction(ISD::SETCC, MVT::f64, Expand);
739
740 // Sparc doesn't have BRCOND either, it has BR_CC.
741 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
742 setOperationAction(ISD::BRIND, MVT::Other, Expand);
743 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
744 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
745 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
746 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
747
748 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
749 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
750 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
751
752 // FIXME: There are instructions available for ATOMIC_FENCE
753 // on SparcV8 and later.
754 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
755 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
756
757 setOperationAction(ISD::FSIN , MVT::f64, Expand);
758 setOperationAction(ISD::FCOS , MVT::f64, Expand);
759 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
760 setOperationAction(ISD::FREM , MVT::f64, Expand);
761 setOperationAction(ISD::FMA , MVT::f64, Expand);
762 setOperationAction(ISD::FSIN , MVT::f32, Expand);
763 setOperationAction(ISD::FCOS , MVT::f32, Expand);
764 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
765 setOperationAction(ISD::FREM , MVT::f32, Expand);
766 setOperationAction(ISD::FMA , MVT::f32, Expand);
767 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
768 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
769 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
770 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
771 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
772 setOperationAction(ISD::ROTL , MVT::i32, Expand);
773 setOperationAction(ISD::ROTR , MVT::i32, Expand);
774 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
775 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
776 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
777 setOperationAction(ISD::FPOW , MVT::f64, Expand);
778 setOperationAction(ISD::FPOW , MVT::f32, Expand);
779
780 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
781 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
782 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
783
784 // FIXME: Sparc provides these multiplies, but we don't have them yet.
785 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
786 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
787
788 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
789
790 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
791 setOperationAction(ISD::VASTART , MVT::Other, Custom);
792 // VAARG needs to be lowered to not do unaligned accesses for doubles.
793 setOperationAction(ISD::VAARG , MVT::Other, Custom);
794
795 // Use the default implementation.
796 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
797 setOperationAction(ISD::VAEND , MVT::Other, Expand);
798 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
799 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
800 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
801
802 // No debug info support yet.
803 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
804
805 setStackPointerRegisterToSaveRestore(SP::O6);
806
807 if (TM.getSubtarget<SparcSubtarget>().isV9())
808 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
809
810 setMinFunctionAlignment(2);
811
812 computeRegisterProperties();
813 }
814
getTargetNodeName(unsigned Opcode) const815 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
816 switch (Opcode) {
817 default: return 0;
818 case SPISD::CMPICC: return "SPISD::CMPICC";
819 case SPISD::CMPFCC: return "SPISD::CMPFCC";
820 case SPISD::BRICC: return "SPISD::BRICC";
821 case SPISD::BRFCC: return "SPISD::BRFCC";
822 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
823 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
824 case SPISD::Hi: return "SPISD::Hi";
825 case SPISD::Lo: return "SPISD::Lo";
826 case SPISD::FTOI: return "SPISD::FTOI";
827 case SPISD::ITOF: return "SPISD::ITOF";
828 case SPISD::CALL: return "SPISD::CALL";
829 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
830 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
831 case SPISD::FLUSHW: return "SPISD::FLUSHW";
832 }
833 }
834
835 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
836 /// be zero. Op is expected to be a target specific node. Used by DAG
837 /// combiner.
computeMaskedBitsForTargetNode(const SDValue Op,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth) const838 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
839 APInt &KnownZero,
840 APInt &KnownOne,
841 const SelectionDAG &DAG,
842 unsigned Depth) const {
843 APInt KnownZero2, KnownOne2;
844 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
845
846 switch (Op.getOpcode()) {
847 default: break;
848 case SPISD::SELECT_ICC:
849 case SPISD::SELECT_FCC:
850 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
851 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
852 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
853 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
854
855 // Only known if known in both the LHS and RHS.
856 KnownOne &= KnownOne2;
857 KnownZero &= KnownZero2;
858 break;
859 }
860 }
861
862 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
863 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
LookThroughSetCC(SDValue & LHS,SDValue & RHS,ISD::CondCode CC,unsigned & SPCC)864 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
865 ISD::CondCode CC, unsigned &SPCC) {
866 if (isa<ConstantSDNode>(RHS) &&
867 cast<ConstantSDNode>(RHS)->isNullValue() &&
868 CC == ISD::SETNE &&
869 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
870 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
871 (LHS.getOpcode() == SPISD::SELECT_FCC &&
872 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
873 isa<ConstantSDNode>(LHS.getOperand(0)) &&
874 isa<ConstantSDNode>(LHS.getOperand(1)) &&
875 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
876 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
877 SDValue CMPCC = LHS.getOperand(3);
878 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
879 LHS = CMPCC.getOperand(0);
880 RHS = CMPCC.getOperand(1);
881 }
882 }
883
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const884 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
885 SelectionDAG &DAG) const {
886 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
887 // FIXME there isn't really any debug info here
888 DebugLoc dl = Op.getDebugLoc();
889 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
890 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
891 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
892
893 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
894 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
895
896 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
897 getPointerTy());
898 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
899 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
900 GlobalBase, RelAddr);
901 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
902 AbsAddr, MachinePointerInfo(), false, false, false, 0);
903 }
904
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const905 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
906 SelectionDAG &DAG) const {
907 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
908 // FIXME there isn't really any debug info here
909 DebugLoc dl = Op.getDebugLoc();
910 const Constant *C = N->getConstVal();
911 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
912 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
913 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
914 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
915 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
916
917 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
918 getPointerTy());
919 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
920 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
921 GlobalBase, RelAddr);
922 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
923 AbsAddr, MachinePointerInfo(), false, false, false, 0);
924 }
925
LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG)926 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
927 DebugLoc dl = Op.getDebugLoc();
928 // Convert the fp value to integer in an FP register.
929 assert(Op.getValueType() == MVT::i32);
930 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
931 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
932 }
933
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG)934 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
935 DebugLoc dl = Op.getDebugLoc();
936 assert(Op.getOperand(0).getValueType() == MVT::i32);
937 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
938 // Convert the int value to FP in an FP register.
939 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
940 }
941
LowerBR_CC(SDValue Op,SelectionDAG & DAG)942 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
943 SDValue Chain = Op.getOperand(0);
944 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
945 SDValue LHS = Op.getOperand(2);
946 SDValue RHS = Op.getOperand(3);
947 SDValue Dest = Op.getOperand(4);
948 DebugLoc dl = Op.getDebugLoc();
949 unsigned Opc, SPCC = ~0U;
950
951 // If this is a br_cc of a "setcc", and if the setcc got lowered into
952 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
953 LookThroughSetCC(LHS, RHS, CC, SPCC);
954
955 // Get the condition flag.
956 SDValue CompareFlag;
957 if (LHS.getValueType() == MVT::i32) {
958 EVT VTs[] = { MVT::i32, MVT::Glue };
959 SDValue Ops[2] = { LHS, RHS };
960 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
961 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
962 Opc = SPISD::BRICC;
963 } else {
964 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
965 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
966 Opc = SPISD::BRFCC;
967 }
968 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
969 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
970 }
971
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG)972 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
973 SDValue LHS = Op.getOperand(0);
974 SDValue RHS = Op.getOperand(1);
975 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
976 SDValue TrueVal = Op.getOperand(2);
977 SDValue FalseVal = Op.getOperand(3);
978 DebugLoc dl = Op.getDebugLoc();
979 unsigned Opc, SPCC = ~0U;
980
981 // If this is a select_cc of a "setcc", and if the setcc got lowered into
982 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
983 LookThroughSetCC(LHS, RHS, CC, SPCC);
984
985 SDValue CompareFlag;
986 if (LHS.getValueType() == MVT::i32) {
987 // subcc returns a value
988 EVT VTs[] = { LHS.getValueType(), MVT::Glue };
989 SDValue Ops[2] = { LHS, RHS };
990 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
991 Opc = SPISD::SELECT_ICC;
992 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
993 } else {
994 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
995 Opc = SPISD::SELECT_FCC;
996 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
997 }
998 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
999 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
1000 }
1001
LowerVASTART(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)1002 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1003 const SparcTargetLowering &TLI) {
1004 MachineFunction &MF = DAG.getMachineFunction();
1005 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
1006
1007 // vastart just stores the address of the VarArgsFrameIndex slot into the
1008 // memory location argument.
1009 DebugLoc dl = Op.getDebugLoc();
1010 SDValue Offset =
1011 DAG.getNode(ISD::ADD, dl, MVT::i32,
1012 DAG.getRegister(SP::I6, MVT::i32),
1013 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
1014 MVT::i32));
1015 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1016 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1),
1017 MachinePointerInfo(SV), false, false, 0);
1018 }
1019
LowerVAARG(SDValue Op,SelectionDAG & DAG)1020 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
1021 SDNode *Node = Op.getNode();
1022 EVT VT = Node->getValueType(0);
1023 SDValue InChain = Node->getOperand(0);
1024 SDValue VAListPtr = Node->getOperand(1);
1025 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1026 DebugLoc dl = Node->getDebugLoc();
1027 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr,
1028 MachinePointerInfo(SV), false, false, false, 0);
1029 // Increment the pointer, VAList, to the next vaarg
1030 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
1031 DAG.getConstant(VT.getSizeInBits()/8,
1032 MVT::i32));
1033 // Store the incremented VAList to the legalized pointer
1034 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
1035 VAListPtr, MachinePointerInfo(SV), false, false, 0);
1036 // Load the actual argument out of the pointer VAList, unless this is an
1037 // f64 load.
1038 if (VT != MVT::f64)
1039 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
1040 false, false, false, 0);
1041
1042 // Otherwise, load it as i64, then do a bitconvert.
1043 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(),
1044 false, false, false, 0);
1045
1046 // Bit-Convert the value to f64.
1047 SDValue Ops[2] = {
1048 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V),
1049 V.getValue(1)
1050 };
1051 return DAG.getMergeValues(Ops, 2, dl);
1052 }
1053
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG)1054 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1055 SDValue Chain = Op.getOperand(0); // Legalize the chain.
1056 SDValue Size = Op.getOperand(1); // Legalize the size.
1057 DebugLoc dl = Op.getDebugLoc();
1058
1059 unsigned SPReg = SP::O6;
1060 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
1061 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
1062 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
1063
1064 // The resultant pointer is actually 16 words from the bottom of the stack,
1065 // to provide a register spill area.
1066 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
1067 DAG.getConstant(96, MVT::i32));
1068 SDValue Ops[2] = { NewVal, Chain };
1069 return DAG.getMergeValues(Ops, 2, dl);
1070 }
1071
1072
getFLUSHW(SDValue Op,SelectionDAG & DAG)1073 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
1074 DebugLoc dl = Op.getDebugLoc();
1075 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
1076 dl, MVT::Other, DAG.getEntryNode());
1077 return Chain;
1078 }
1079
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG)1080 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1081 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1082 MFI->setFrameAddressIsTaken(true);
1083
1084 EVT VT = Op.getValueType();
1085 DebugLoc dl = Op.getDebugLoc();
1086 unsigned FrameReg = SP::I6;
1087
1088 uint64_t depth = Op.getConstantOperandVal(0);
1089
1090 SDValue FrameAddr;
1091 if (depth == 0)
1092 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1093 else {
1094 // flush first to make sure the windowed registers' values are in stack
1095 SDValue Chain = getFLUSHW(Op, DAG);
1096 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
1097
1098 for (uint64_t i = 0; i != depth; ++i) {
1099 SDValue Ptr = DAG.getNode(ISD::ADD,
1100 dl, MVT::i32,
1101 FrameAddr, DAG.getIntPtrConstant(56));
1102 FrameAddr = DAG.getLoad(MVT::i32, dl,
1103 Chain,
1104 Ptr,
1105 MachinePointerInfo(), false, false, false, 0);
1106 }
1107 }
1108 return FrameAddr;
1109 }
1110
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG)1111 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
1112 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1113 MFI->setReturnAddressIsTaken(true);
1114
1115 EVT VT = Op.getValueType();
1116 DebugLoc dl = Op.getDebugLoc();
1117 unsigned RetReg = SP::I7;
1118
1119 uint64_t depth = Op.getConstantOperandVal(0);
1120
1121 SDValue RetAddr;
1122 if (depth == 0)
1123 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
1124 else {
1125 // flush first to make sure the windowed registers' values are in stack
1126 SDValue Chain = getFLUSHW(Op, DAG);
1127 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
1128
1129 for (uint64_t i = 0; i != depth; ++i) {
1130 SDValue Ptr = DAG.getNode(ISD::ADD,
1131 dl, MVT::i32,
1132 RetAddr,
1133 DAG.getIntPtrConstant((i == depth-1)?60:56));
1134 RetAddr = DAG.getLoad(MVT::i32, dl,
1135 Chain,
1136 Ptr,
1137 MachinePointerInfo(), false, false, false, 0);
1138 }
1139 }
1140 return RetAddr;
1141 }
1142
1143 SDValue SparcTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const1144 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1145 switch (Op.getOpcode()) {
1146 default: llvm_unreachable("Should not custom lower this!");
1147 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1148 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1149 case ISD::GlobalTLSAddress:
1150 llvm_unreachable("TLS not implemented for Sparc.");
1151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1152 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1153 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1154 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1155 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1156 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1157 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
1158 case ISD::VAARG: return LowerVAARG(Op, DAG);
1159 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1160 }
1161 }
1162
1163 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const1164 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1165 MachineBasicBlock *BB) const {
1166 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1167 unsigned BROpcode;
1168 unsigned CC;
1169 DebugLoc dl = MI->getDebugLoc();
1170 // Figure out the conditional branch opcode to use for this select_cc.
1171 switch (MI->getOpcode()) {
1172 default: llvm_unreachable("Unknown SELECT_CC!");
1173 case SP::SELECT_CC_Int_ICC:
1174 case SP::SELECT_CC_FP_ICC:
1175 case SP::SELECT_CC_DFP_ICC:
1176 BROpcode = SP::BCOND;
1177 break;
1178 case SP::SELECT_CC_Int_FCC:
1179 case SP::SELECT_CC_FP_FCC:
1180 case SP::SELECT_CC_DFP_FCC:
1181 BROpcode = SP::FBCOND;
1182 break;
1183 }
1184
1185 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
1186
1187 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1188 // control-flow pattern. The incoming instruction knows the destination vreg
1189 // to set, the condition code register to branch on, the true/false values to
1190 // select between, and a branch opcode to use.
1191 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1192 MachineFunction::iterator It = BB;
1193 ++It;
1194
1195 // thisMBB:
1196 // ...
1197 // TrueVal = ...
1198 // [f]bCC copy1MBB
1199 // fallthrough --> copy0MBB
1200 MachineBasicBlock *thisMBB = BB;
1201 MachineFunction *F = BB->getParent();
1202 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1203 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1204 F->insert(It, copy0MBB);
1205 F->insert(It, sinkMBB);
1206
1207 // Transfer the remainder of BB and its successor edges to sinkMBB.
1208 sinkMBB->splice(sinkMBB->begin(), BB,
1209 llvm::next(MachineBasicBlock::iterator(MI)),
1210 BB->end());
1211 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1212
1213 // Add the true and fallthrough blocks as its successors.
1214 BB->addSuccessor(copy0MBB);
1215 BB->addSuccessor(sinkMBB);
1216
1217 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
1218
1219 // copy0MBB:
1220 // %FalseValue = ...
1221 // # fallthrough to sinkMBB
1222 BB = copy0MBB;
1223
1224 // Update machine-CFG edges
1225 BB->addSuccessor(sinkMBB);
1226
1227 // sinkMBB:
1228 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1229 // ...
1230 BB = sinkMBB;
1231 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1232 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1233 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1234
1235 MI->eraseFromParent(); // The pseudo instruction is gone now.
1236 return BB;
1237 }
1238
1239 //===----------------------------------------------------------------------===//
1240 // Sparc Inline Assembly Support
1241 //===----------------------------------------------------------------------===//
1242
1243 /// getConstraintType - Given a constraint letter, return the type of
1244 /// constraint it is for this target.
1245 SparcTargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const1246 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1247 if (Constraint.size() == 1) {
1248 switch (Constraint[0]) {
1249 default: break;
1250 case 'r': return C_RegisterClass;
1251 }
1252 }
1253
1254 return TargetLowering::getConstraintType(Constraint);
1255 }
1256
1257 std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string & Constraint,EVT VT) const1258 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1259 EVT VT) const {
1260 if (Constraint.size() == 1) {
1261 switch (Constraint[0]) {
1262 case 'r':
1263 return std::make_pair(0U, &SP::IntRegsRegClass);
1264 }
1265 }
1266
1267 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1268 }
1269
1270 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const1271 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1272 // The Sparc target isn't yet aware of offsets.
1273 return false;
1274 }
1275