| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 40 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I]; in ehDataReg()
53 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; in emitPrologue()
54 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; in emitPrologue()
55 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in emitPrologue()
56 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in emitPrologue()
106 if (!STI.isLittle()) in emitPrologue()
121 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue()
169 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; in emitEpilogue()
170 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; in emitEpilogue()
171 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in emitEpilogue()
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| D | MipsSEInstrInfo.cpp | 259 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in adjustStackPtr() local
261 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in adjustStackPtr()
262 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; in adjustStackPtr()
279 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in loadImmediate() local
281 unsigned Size = STI.isABI_N64() ? 64 : 32; in loadImmediate()
282 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; in loadImmediate()
283 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate()
284 const TargetRegisterClass *RC = STI.isABI_N64() ? in loadImmediate()
368 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in ExpandEhReturn() local
369 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in ExpandEhReturn()
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| D | MipsFrameLowering.h | 26 const MipsSubtarget &STI;
31 sti.hasMips64() ? 16 : 8), STI(sti) {} in MipsFrameLowering()
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| D | MipsSEFrameLowering.h | 23 explicit MipsSEFrameLowering(const MipsSubtarget &STI) in MipsSEFrameLowering() argument
24 : MipsFrameLowering(STI) {} in MipsSEFrameLowering()
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| D | Mips16FrameLowering.h | 22 explicit Mips16FrameLowering(const MipsSubtarget &STI) in Mips16FrameLowering() argument
23 : MipsFrameLowering(STI) {} in Mips16FrameLowering()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in MipsDisassemblerBase() argument
38 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {} in MipsDisassemblerBase()
55 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in MipsDisassembler() argument
57 MipsDisassemblerBase(STI, Info, bigEndian) {} in MipsDisassembler()
74 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in Mips64Disassembler() argument
76 MipsDisassemblerBase(STI, Info, bigEndian) {} in Mips64Disassembler()
198 const MCSubtargetInfo &STI) { in createMipsDisassembler() argument
199 return new MipsDisassembler(STI, T.createMCRegInfo(""), true); in createMipsDisassembler()
204 const MCSubtargetInfo &STI) { in createMipselDisassembler() argument
205 return new MipsDisassembler(STI, T.createMCRegInfo(""), false); in createMipselDisassembler()
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | AMDGPUMCTargetDesc.cpp | 70 const MCSubtargetInfo &STI) { in createAMDGPUMCInstPrinter() argument
76 const MCSubtargetInfo &STI, in createAMDGPUMCCodeEmitter() argument
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { in createAMDGPUMCCodeEmitter()
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); in createAMDGPUMCCodeEmitter()
81 return createR600MCCodeEmitter(MCII, MRI, STI, Ctx); in createAMDGPUMCCodeEmitter()
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| D | SIMCCodeEmitter.cpp | 42 const MCSubtargetInfo &STI; member in __anon8c7c958b0111::SIMCCodeEmitter
54 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { } in SIMCCodeEmitter()
71 const MCSubtargetInfo &STI, in createSIMCCodeEmitter() argument
73 return new SIMCCodeEmitter(MCII, MRI, STI, Ctx); in createSIMCCodeEmitter()
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| D | AMDGPUMCTargetDesc.h | 34 const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 61 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU, in LLVMCreateDisasmCPU() local
63 if (!STI) in LLVMCreateDisasmCPU()
72 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI); in LLVMCreateDisasmCPU()
80 *MAI, *MII, *MRI, *STI); in LLVMCreateDisasmCPU()
87 STI, MII, Ctx, DisAsm, IP); in LLVMCreateDisasmCPU()
212 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); in LLVMSetDisasmOptions() local
216 AsmPrinterVariant, *MAI, *MII, *MRI, *STI); in LLVMSetDisasmOptions()
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| /external/llvm/include/llvm/MC/ |
| D | MCDisassembler.h | 56 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0), in MCDisassembler() argument
58 STI(STI), CommentStream(0) {} in MCDisassembler()
100 const MCSubtargetInfo &STI;
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 58 STI = sti; in init()
60 STI->initInstrItins(InstrItins); in init()
138 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
218 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
263 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeInstrLatency()
301 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc), in computeOutputLatency()
302 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) { in computeOutputLatency()
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| D | LLVMTargetMachine.cpp | 164 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitFile() local
172 Context->getRegisterInfo(), STI); in addPassesToEmitFile()
178 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitFile() local
179 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI, STI, in addPassesToEmitFile()
199 STI, *Context); in addPassesToEmitFile()
271 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitMC() local
273 STI, *Ctx); in addPassesToEmitMC()
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| /external/llvm/include/llvm/CodeGen/ |
| D | TargetSchedule.h | 37 const TargetSubtargetInfo *STI; variable
44 TargetSchedModel(): STI(0), TII(0) {} in TargetSchedModel()
110 return STI->getWriteProcResBegin(SC); in getWriteProcResBegin()
113 return STI->getWriteProcResEnd(SC); in getWriteProcResEnd()
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| /external/llvm/include/llvm/Support/ |
| D | TargetRegistry.h | 98 typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
101 const MCSubtargetInfo &STI);
107 const MCSubtargetInfo &STI);
110 const MCSubtargetInfo &STI,
356 MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, in createMCAsmParser() argument
360 return MCAsmParserCtorFn(STI, Parser); in createMCAsmParser()
371 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const { in createMCDisassembler() argument
374 return MCDisassemblerCtorFn(*this, STI); in createMCDisassembler()
381 const MCSubtargetInfo &STI) const { in createMCInstPrinter() argument
384 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, STI); in createMCInstPrinter()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 501 bool Is64Bit = STI.is64Bit(); in getCompactUnwindEncoding()
662 bool Is64Bit = STI.is64Bit(); in emitPrologue()
663 bool IsLP64 = STI.isTarget64BitLP64(); in emitPrologue()
664 bool IsWin64 = STI.isTargetWin64(); in emitPrologue()
665 bool UseLEA = STI.useLeaForSP(); in emitPrologue()
877 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) { in emitPrologue()
882 if (STI.isTargetCygMing()) in emitPrologue()
888 } else if (STI.isTargetCygMing()) in emitPrologue()
984 if (STI.getTargetTriple().isMacOSX() && in emitPrologue()
985 !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) in emitPrologue()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti), in ARMBaseRegisterInfo()
49 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
66 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCalleeSavedRegs()
73 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCallPreservedMask()
96 if (STI.isR9Reserved()) in getReservedRegs()
99 if (!STI.hasVFP3() || STI.hasD16()) { in getReservedRegs()
158 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); in getRegPressureLimit()
248 if (!STI.isLikeA9()) in avoidWriteAfterWrite()
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| D | ARMHazardRecognizer.h | 33 const ARMSubtarget &STI; variable
45 TRI(tri), STI(sti), LastMI(0) {} in ARMHazardRecognizer()
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| D | Thumb1InstrInfo.cpp | 24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) in Thumb1InstrInfo() argument
25 : ARMBaseInstrInfo(STI), RI(*this, STI) { in Thumb1InstrInfo()
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 35 const MCSubtargetInfo &STI; member in __anon517ab50a0111::PPCMCCodeEmitter
41 : STI(sti), TT(STI.getTargetTriple()) { in PPCMCCodeEmitter()
47 return (STI.getFeatureBits() & PPC::Feature64Bit) != 0; in is64BitMode()
108 const MCSubtargetInfo &STI, in createPPCMCCodeEmitter() argument
110 return new PPCMCCodeEmitter(MCII, STI, Ctx); in createPPCMCCodeEmitter()
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.h | 31 MBlazeDisassembler(const MCSubtargetInfo &STI) : in MBlazeDisassembler() argument
32 MCDisassembler(STI) { in MBlazeDisassembler()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeFrameLowering.h | 25 const MBlazeSubtarget &STI;
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) { in MBlazeFrameLowering()
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| /external/llvm/tools/llvm-mc/ |
| D | llvm-mc.cpp | 325 MCAsmInfo &MAI, MCSubtargetInfo &STI) { in AssembleInput() argument
328 OwningPtr<MCTargetAsmParser> TAP(TheTarget->createMCAsmParser(STI, *Parser)); in AssembleInput()
428 STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); in main() local
433 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI); in main()
437 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); in main()
451 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); in main()
465 Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI); in main()
482 Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str, in main()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) { in MSP430FrameLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) { in HexagonFrameLowering()
|